You have to be careful with terminology. There is compiling to a software executable, which you then execute to simulate your design. Then there is compiling

You have to be careful with terminology. There is compiling to a software executable, which you then execute to simulate your design. Then there is compiling to a bitstream that goes into an FPGA to implement the design in real hardware. This type of compilation is really a multi-step process of synthesis, place, and route. Compiling for simulation usually pretty quick. Depending on how many clock cycles of stimulus coded into your simulation, the execution of the simulation can be also be pretty quick or hours and hours long. Compiling for the FPGA usually takes much longer than compilation for simulation. Running the same number of clock cycles as your simulation is much much faster in using real hardware (FPGA) than the simulation. Reading the description in TFA, it sounds like this tool does both types of compiles. I hope I have more time to play with it soon, because it sounds like it even offers to produce a complete software/hardware system out of your verilog (not all legal verilog syntax can be compiled to hardware, but it can all be compiled to a software executable).