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This reads mostly like a pretty PR-fed puff piece version of the announcements of the Cascade Lake MCM that HN discussed last week [1], and again the Anandtech
by xoa 8y ago
This reads mostly like a pretty PR-fed puff piece version of the announcements of the Cascade Lake MCM that HN discussed last week [1], and again the Anandtech piece [2] is more interesting as well as more skeptical. Granted it hasn't been out for deep 3rd party testing and inspection yet, but from what was announced after chewing on it a week I think this still feels like a desperate rapid response move from Intel being caught off guard rather then the result of a long planned strategy. It feels too much like they took what they could given yield and TDP and simply applied a ton of glue they already had until they kind of worked together in a single one-off product that could at least produce headline numbers more competitive to AMD. No EMIB, no range of products up and down the spectrum with smaller Xeon modules designed for combination, just this ginormous 300W one-off with UPI. In fact this article seems to have a bit of new info on that:
>*"that leverages one of the three UltraPath Interconnect (UPI) links to hook the two physical chips together to create what essentially is a 48-core socket with 12 memory controllers"
If that's correct and it's 3 UPI, then presumably it'd be the square config so unlike a normal 4P system each processor does not necessarily have a direct link to all others, they may have to go through multiple hops. It definitely would not be "essentially a 48-core" at all since it'd complicate memory access patterns significantly wouldn't it? If that's the layout the potential for benchmark cherry picking and specific optimization that isn't applicable to other workloads seems even higher then normal.
AMD got a leap on Intel last with x86-64 because they didn't want to do that on the desktop, maybe MCM will turn out to be something a little like that (though less dramatic) as well given the realities of increasing difficulties in large single chip fabrication. It'd be interesting if internally Intel is rethinking that but this doesn't seem like "doubling down" so much as a first scramble.
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1: https://news.ycombinator.com/item?id=18389373 https://news.ycombinator.com/item?id=18389373
2: https://www.anandtech.com/show/13535/intel-goes-for-48cores-cascade-ap https://www.anandtech.com/show/13535/intel-goes-for-48cores-...
- zamadatix 8y ago> If that's correct and it's 3 UPI, then presumably it'd be the square config so unlike a normal 4P system each processor does not necessarily have a direct link to all others Yeah but their target isn't to compete with a 48 core monolithic CPU it was to compete with AMDs EPYC CPUs which have even less uniform connectivity between sockets (3 per used for in socket interconnect and only 1 used to connect to the other socket). Unfortunately for Intel AMD is still going to be a step ahead this generation with the chiplet + IO module architecture IMO.
- Symmetry 8y agoIf it had been a considered move, planned well in advance they would have designed some Xeon dies to use EMIB interconnects rather than making due with the designs they had on hand. [1]https://www.intel.com/content/www/us/en/foundry/emib.html https://www.intel.com/content/www/us/en/foundry/emib.html
- rbanffy 8y agoUnless they consider this a transitional generation to future MCP processor modules. Launch early, assess market fit and plan accordingly. Intel did differently with Phi and it didn't quite work the way they (and I) expected.
- saltcured 8y agoAlso, this MCM approach is a common Intel strategy. They did it for early dual core CPUs (Pentium D) and again with early quad core CPUs (e.g. Q6600 was basically two E6600 chips).
- rbanffy 8y ago> It definitely would not be "essentially a 48-core" at all since it'd complicate memory access patterns significantly My belief is that it behaves similarly to a 4-way 12-core machine using less real estate for the CPU. Even though memory will occupy the same amount of space, I suspect we may see it on high-end workstation-class machines by the likes of Supermicro and Gigabyte.