I'm really curious about cache on the IO die. Ian Cutress of Anandtech said Rome is ~ 1000 mm² in total. [0] Based on that and the pictures of the Rome die that

I'm really curious about cache on the IO die. Ian Cutress of Anandtech said Rome is ~ 1000 mm² in total. [0] Based on that and the pictures of the Rome die that were shown some users [1] estimated the size of the IO die to be 387 - 407 mm². - Zen 1 (8 cores) with IO is 213 mm². - the Zen 2 core only chiplets are estimated to be around 70 mm². - if we assume IO scales as well as the rest (which it doesn't) Zen 1 would be ~106 mm² on 7nm. - let's just say the difference between Zen 2 core only chiplets and the imaginary Zen 1 on 7nm is the size of the IO per Zeppelin die => ~36 mm² - now double the area again because the IO die is on 14nm => 72 mm² - now quadruple the size because we have 8 memory channels and 128 PCIe 4.0 lanes => 288 mm² Going by my flawed layman estimation this would mean we still have a budget of ~100 mm² for additional functionality. Either PCIe 4.0 takes much more space than PCIe 3.0, they have some secret sauce in there, or maybe just a large L4 cache. If they use EDRAM instead of SRAM like Intel did with some of their Broadwell and Skylake CPUs they could probably fit quite a bit cache in this area. Intel used 128 MB EDRAM fabbed on a 22nm node which required 84mm ² [2] [0] https://twitter.com/IanCutress/status/1059924863014653958 https://twitter.com/IanCutress/status/1059924863014653958 [1] https://old.reddit.com/r/Amd/comments/9uscqu/epyc_and_epyc_2_dies_compared/e96m4yv/ https://old.reddit.com/r/Amd/comments/9uscqu/epyc_and_epyc_2... [2] https://www.anandtech.com/show/6993/intel-iris-pro-5200-graphics-review-core-i74950hq-tested/3 https://www.anandtech.com/show/6993/intel-iris-pro-5200-grap...