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Not really. E.g. the AMD ZEN+ moved to a 12nm process but kept both transistor count and die size constant. They instead used the headroom to space features out
by pdpi 8y ago
Not really. E.g. the AMD ZEN+ moved to a 12nm process but kept both transistor count and die size constant. They instead used the headroom to space features out and improve cooling.
- the8472 8y agoYou could still specify the maximum possible transistor density for the process. It doesn't mean a concrete design actually has to use it. Or make it an SRAM bit, because caches take up the bulk of the area anyway.
- blattimwind 8y agoPretty much equivalent to SRAM cell density, which you can measure under a microscope.
- sevensor 8y agoSpeaking of SRAM, it's interesting how much effort is devoted to keeping the logic busy so they don't have to spend chip area on cache.
- monocasa 8y agoI think the HDL guys were running around with their hair on fire for Spectre bugs, hence why it was a straight transistor shrink with next to no logic changes. It's previously unheard of to not take advantage of a process shrink with logic changes; so much of your logic decisions are ultimately rooted in the process node.