Anandtech's article has more technical details and discussion: https://www.anandtech.com/show/13535/intel-goes-for-48cores-cascade-ap https://www.anandtech.com

Anandtech's article has more technical details and discussion: https://www.anandtech.com/show/13535/intel-goes-for-48cores-cascade-ap https://www.anandtech.com/show/13535/intel-goes-for-48cores-... The most pertinent technical questions and concern seems to be around the interconnects, since inter-die bandwidth and latency are big factors in performance. I think the major surprise/disappointment there is that within the MCM they apparently are not using their Embedded Multi-die Interconnect Bridge (EMIB) which was supposed to be their next-gen interposer replacement. They have been pretty flowery about it, right up to on the official page [1] having fun with a Star Wars riff and calling EMIB "an Elegant Interconnect for a More Civilized Age". Looks like it's all UPI here though. According to Cutress it also isn't clear exactly how many UPI link are used between the two sockets. It's not like MCM usage is some necessarily exotic thing, IBM has been doing it in various forms including for POWER forever. Even beyond TDP however Intel's approach here definitely seems kind of "odd" to put it neutrally. I think if this is going to be a major part of their strategy going forward they'll need a different approach, but for that very reason I wonder if this is more of a one-off placeholder? ---- 1: https://www.intel.com/content/www/us/en/foundry/emib.html https://www.intel.com/content/www/us/en/foundry/emib.html