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For anyone that isn't aware, this is a brilliant tool. I just wish it supported ARM hardware (as far as I remember there are some interrupts that clobber state,

For anyone that isn't aware, this is a brilliant tool. I just wish it supported ARM hardware (as far as I remember there are some interrupts that clobber state, so this can't be used. Please fill in the details if anyone remembers).

pm215 8y ago
The upstream issue with discussion about Arm support is https://github.com/mozilla/rr/issues/1373 https://github.com/mozilla/rr/issues/1373 -- the underlying problem is that rr's design assumes that if you execute N instructions you'll always deterministically end up in the same place. In architectures which implement atomics via a load-linked/store-conditional loop (including Alpha, Arm, MIPS, PPC,...) this isn't true, because differences at the OS level (eg timing of other interrupts or process scheduling) could cause an ll/sc loop to loop round more often. It's not clear how this could be addressed, because it's pretty deeply baked into rr's design.
- roca 8y ago
  CPU support for trapping on a failed LL/SC would suffice.
  - pm215 8y ago
    Do you have a sketch of how that would work? It seems plausible but I haven't thought through the details. Issue 1373 suggests a perf counter of failed-SC events and looking at "branches taken - failed_SC", which I'm definitely sceptical would be reliable.
    - roca 8y ago
      Sure, I just added it here: https://github.com/mozilla/rr/issues/1373#issuecomment-436270586 https://github.com/mozilla/rr/issues/1373#issuecomment-43627...
worldgeek 8y ago
TLDR; If you want RR on ARM try UndoDB (which has a different instrumentation method). RR needs an accurate count of "retired instructions" to replay correctly. ARM has non-deterministic behaviour for this count because an instruction may fail for example due to a cache miss or a hardware interrupt,the instruction would be re-tried of course but the retired instruction count for a code path run multiple times can vary even if identical branches are taken. Longer / better description at this URL. https://github.com/mozilla/rr/issues/1373 https://github.com/mozilla/rr/issues/1373

pm215 8y ago

The upstream issue with discussion about Arm support is https://github.com/mozilla/rr/issues/1373 https://github.com/mozilla/rr/issues/1373 -- the underlying problem is that rr's design assumes that if you execute N instructions you'll always deterministically end up in the same place. In architectures which implement atomics via a load-linked/store-conditional loop (including Alpha, Arm, MIPS, PPC,...) this isn't true, because differences at the OS level (eg timing of other interrupts or process scheduling) could cause an ll/sc loop to loop round more often. It's not clear how this could be addressed, because it's pretty deeply baked into rr's design.

roca 8y ago
CPU support for trapping on a failed LL/SC would suffice.
- pm215 8y ago
  Do you have a sketch of how that would work? It seems plausible but I haven't thought through the details. Issue 1373 suggests a perf counter of failed-SC events and looking at "branches taken - failed_SC", which I'm definitely sceptical would be reliable.
  - roca 8y ago
    Sure, I just added it here: https://github.com/mozilla/rr/issues/1373#issuecomment-436270586 https://github.com/mozilla/rr/issues/1373#issuecomment-43627...

worldgeek 8y ago

TLDR; If you want RR on ARM try UndoDB (which has a different instrumentation method). RR needs an accurate count of "retired instructions" to replay correctly. ARM has non-deterministic behaviour for this count because an instruction may fail for example due to a cache miss or a hardware interrupt,the instruction would be re-tried of course but the retired instruction count for a code path run multiple times can vary even if identical branches are taken. Longer / better description at this URL. https://github.com/mozilla/rr/issues/1373 https://github.com/mozilla/rr/issues/1373