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I don't understand the hype around RISC-V. The single most important bottleneck in general Computing nowadays is memory latency. However code density of RISC-V

by sprash 8y ago

I don't understand the hype around RISC-V. The single most important bottleneck in general Computing nowadays is memory latency. However code density of RISC-V is absolutely underwhelming and does not even beat ARM-Thumb which is literally decades old. If it has to be RISC and open why not using something that already has an existing infrastructure and is well established. E.g. Fully open source implementations of the SPARC architecture exist for a long time already.

rwmj 8y ago
Code density is claimed to be similar to x86 and better than ARM with thumb, see the bottom of this slide: https://www.youtube.com/watch?v=Ii_pEXKKYUg&feature=youtu.be&t=13m55s https://www.youtube.com/watch?v=Ii_pEXKKYUg&feature=youtu.be... More information on the original design (not quite the final design) of the Compressed extension can be found in the original research paper: https://people.eecs.berkeley.edu/~krste/papers/waterman-ms.pdf https://people.eecs.berkeley.edu/~krste/papers/waterman-ms.p... And ... SPARC. Seriously? Register windows were a failed experiment.
- sprash 8y ago
  In the research paper it literally says that Thump-2 is 7% smaller than RVC, which is in agreement with my personal experiments. Also, how are register windows a failure?
  - jecel 8y ago
    The Sparc V8 running Solaris took hundreds of clock cycles to handle traps, so some languages actually performed better by ignoring the register windows and avoiding the overflow/underflow traps. This one bad implementation hurt the reputation of the idea in general even though Sparc V9 improved this significantly. People also like to point out that the original NIOS processor from Altera had register windows but they were eliminated from the NIOS II. What they forget to mention is that Altera claimed this allowed them to make a smaller core "without hurting performance too much". Which means that the register windows version was faster, not slower like they want to imply.
  - rwmj 8y ago
    The research paper is not the final RVC extension (although it was derived from that research). The video covers the RVC extension as it was implemented.
schaefer 8y ago
Consider reading the About page [1]. In summary: RISC‑V is a free and open ISA. They aren't claiming groundbreaking hardware performance and/or design. They are claiming groundbreaking lack of legal/NDA entanglement. Special bonus/origin story: completely open for academic research and tinkering. [1] https://www.sifive.com/why https://www.sifive.com/why
nickik 8y ago
Nobody that works on RISC-V believes that a mew ISA will change the game in terms of performance. That's not really the main goal. It is false that density is 'underwhelming'. Thumb while old is extrmly good and specifically designed for density. With Thumb on 32Bit they are about on par, but on 64Bit RISC-V wins against ARM. ARM 32 Bit is really the only thing that can compete. They had good reason for not using something that exists. SPARC has one open specification but the version after that is not open anymore. It has a number of technical problems for the modern world. There is not enough open software and hardware in to make the argument for adopting it wothwhile. Furthermore its a monolitic and RISC-V was from the ground up designed as modular ISA where the same basic software stack can run on deep embeded and HPC.
- sprash 8y ago
  > Nobody that works on RISC-V believes that a mew ISA will change the game in terms of performance. That's not really the main goal. And this is why they will fail. RISC-V suffers hugely from NIHS and would have no chance against any competition in a real market without that artificial hype. They need to get better. > They had good reason for not using something that exists. SPARC has one open specification but the version after that is not open anymore. The fully GPL licensed OpenSPARC T2 is more advanced than anything RISC-V has to offer even though it is ten years old. Why reinvent the wheel when you can build on top of existing solutions that has proven itself on millions of machines including two top 100 Computer clusters. > RISC-V was from the ground up designed as modular ISA where the same basic software stack can run on deep embeded and HPC. This is also true for SPARC.
  - nickik 8y ago
    > And this is why they will fail. RISC-V suffers hugely from NIHS and would have no chance against any competition in a real market without that artificial hype. They need to get better. I'm sorry but that is nonsense. An ISA (unless its a utterly terrible one) simply is not what determains performance. RISC-V will be useful for performance because you can make a good cores far easier then if you used any other ISA. RISC-V is well optimized for performance and future standard extensions will give the micro-architect a lot of options to make performant chips. Furthermore, why do they suffer from NIHS? The whole ISA is quite literally designed to be a relatively conservative design that specifically build on the knowledge gained by others in the last 30 years. Its the exact opposite of NIHS. The only NIHS is that you are complaining about is that they did something new at all. > The fully GPL licensed OpenSPARC T2 is more advanced than anything RISC-V has to offer even though it is ten years old. Why reinvent the wheel when you can build on top of existing solutions that has proven itself on millions of machines including two top 100 Computer clusters. SPARC is now owned by Oracle and only SPARC V8 is an open standard. The OpenSPARC T2 is v9. Do you really think its good to start a new revolutionary compute project on something so strongly tied to Oracle? You are aware that some of the same people who helped design SPARC also designed RISC-V. You can listen to their explanations of why they didn't want SPARC, specially not for a what is designed to be a universal ISA. > This is also true for SPARC. No its not. SPARC is not a modular ISA in the same way RISC-V is and the RISC-V believe that a modular ISA will be needed.
dingosity 8y ago
Meh. Compressed to RISC-V is close to thumb2 in density if you write everything in assembly. The current gcc compiler does generate some underwhelming code, but it's a lot better than it was a year ago and chatter on the list is there's still improvements to make, so the trend is in the right direction.

by sprash 8y ago

rwmj 8y ago

Code density is claimed to be similar to x86 and better than ARM with thumb, see the bottom of this slide: https://www.youtube.com/watch?v=Ii_pEXKKYUg&feature=youtu.be&t=13m55s https://www.youtube.com/watch?v=Ii_pEXKKYUg&feature=youtu.be... More information on the original design (not quite the final design) of the Compressed extension can be found in the original research paper: https://people.eecs.berkeley.edu/~krste/papers/waterman-ms.pdf https://people.eecs.berkeley.edu/~krste/papers/waterman-ms.p... And ... SPARC. Seriously? Register windows were a failed experiment.

sprash 8y ago
In the research paper it literally says that Thump-2 is 7% smaller than RVC, which is in agreement with my personal experiments. Also, how are register windows a failure?
- jecel 8y ago
  The Sparc V8 running Solaris took hundreds of clock cycles to handle traps, so some languages actually performed better by ignoring the register windows and avoiding the overflow/underflow traps. This one bad implementation hurt the reputation of the idea in general even though Sparc V9 improved this significantly. People also like to point out that the original NIOS processor from Altera had register windows but they were eliminated from the NIOS II. What they forget to mention is that Altera claimed this allowed them to make a smaller core "without hurting performance too much". Which means that the register windows version was faster, not slower like they want to imply.
- rwmj 8y ago
  The research paper is not the final RVC extension (although it was derived from that research). The video covers the RVC extension as it was implemented.

schaefer 8y ago

Consider reading the About page [1]. In summary: RISC‑V is a free and open ISA. They aren't claiming groundbreaking hardware performance and/or design. They are claiming groundbreaking lack of legal/NDA entanglement. Special bonus/origin story: completely open for academic research and tinkering. [1] https://www.sifive.com/why https://www.sifive.com/why

nickik 8y ago

Nobody that works on RISC-V believes that a mew ISA will change the game in terms of performance. That's not really the main goal. It is false that density is 'underwhelming'. Thumb while old is extrmly good and specifically designed for density. With Thumb on 32Bit they are about on par, but on 64Bit RISC-V wins against ARM. ARM 32 Bit is really the only thing that can compete. They had good reason for not using something that exists. SPARC has one open specification but the version after that is not open anymore. It has a number of technical problems for the modern world. There is not enough open software and hardware in to make the argument for adopting it wothwhile. Furthermore its a monolitic and RISC-V was from the ground up designed as modular ISA where the same basic software stack can run on deep embeded and HPC.

sprash 8y ago
> Nobody that works on RISC-V believes that a mew ISA will change the game in terms of performance. That's not really the main goal. And this is why they will fail. RISC-V suffers hugely from NIHS and would have no chance against any competition in a real market without that artificial hype. They need to get better. > They had good reason for not using something that exists. SPARC has one open specification but the version after that is not open anymore. The fully GPL licensed OpenSPARC T2 is more advanced than anything RISC-V has to offer even though it is ten years old. Why reinvent the wheel when you can build on top of existing solutions that has proven itself on millions of machines including two top 100 Computer clusters. > RISC-V was from the ground up designed as modular ISA where the same basic software stack can run on deep embeded and HPC. This is also true for SPARC.
- nickik 8y ago
  > And this is why they will fail. RISC-V suffers hugely from NIHS and would have no chance against any competition in a real market without that artificial hype. They need to get better. I'm sorry but that is nonsense. An ISA (unless its a utterly terrible one) simply is not what determains performance. RISC-V will be useful for performance because you can make a good cores far easier then if you used any other ISA. RISC-V is well optimized for performance and future standard extensions will give the micro-architect a lot of options to make performant chips. Furthermore, why do they suffer from NIHS? The whole ISA is quite literally designed to be a relatively conservative design that specifically build on the knowledge gained by others in the last 30 years. Its the exact opposite of NIHS. The only NIHS is that you are complaining about is that they did something new at all. > The fully GPL licensed OpenSPARC T2 is more advanced than anything RISC-V has to offer even though it is ten years old. Why reinvent the wheel when you can build on top of existing solutions that has proven itself on millions of machines including two top 100 Computer clusters. SPARC is now owned by Oracle and only SPARC V8 is an open standard. The OpenSPARC T2 is v9. Do you really think its good to start a new revolutionary compute project on something so strongly tied to Oracle? You are aware that some of the same people who helped design SPARC also designed RISC-V. You can listen to their explanations of why they didn't want SPARC, specially not for a what is designed to be a universal ISA. > This is also true for SPARC. No its not. SPARC is not a modular ISA in the same way RISC-V is and the RISC-V believe that a modular ISA will be needed.

dingosity 8y ago

Meh. Compressed to RISC-V is close to thumb2 in density if you write everything in assembly. The current gcc compiler does generate some underwhelming code, but it's a lot better than it was a year ago and chatter on the list is there's still improvements to make, so the trend is in the right direction.