Ok, let's get started. We need an abstract simulator front end, and to be able to connect that simulator front end to both Verilog and VHDL - almost like a simu

Ok, let's get started. We need an abstract simulator front end, and to be able to connect that simulator front end to both Verilog and VHDL - almost like a simulator IR language, and have that language cover productions from both VHDL and Verilog. There's some recent Verilator optimazations to look at, but all that stuff comes later. V0.0 should probably just have a simple message pump for delta cycle emissions. I'll start seeing if I can gather some literature on this.