3 ms·
Verilog may be horrible and SystemVerilog may not be perfect (its a hell of a lot better than Verilog though) but there are innumerable projects written in thes
by jacoblambda 8y ago
Verilog may be horrible and SystemVerilog may not be perfect (its a hell of a lot better than Verilog though) but there are innumerable projects written in these languages that could benefit from or be a benefit to others if they had better interoperability.