I see what you mean by delta simulator. However most of the testbench code inside your “initial” block should be run by verilator, you would barely even need to

I see what you mean by delta simulator. However most of the testbench code inside your “initial” block should be run by verilator, you would barely even need to write 5 lines of C++ code if you already have a verilog testbench. Icarus Verilog maybe a good alternative as well. All that said, I am interested in developing an FOSS parser+delta simulator. Any pointers on where to start?