4 ms·

I thought Verilator sort of does that.

• analognoise 8y ago
  Verilator is a cycle simulator - not a delta simulator; it can't handle delay elements. Also, it won't do VHDL (there was some code there to do a small amount of it contributed about 9 years ago, but it's been dormant since, as I understand it). It is driven by C/C++ - which is a huge stumbling block, especially if you have a repository of code already running in VHDL/Verilog. We see an infinite number of people inventing toy languages and things, but nobody who is solving something FOSS actually needs if we're all going to be making our own chips with free tools: Mixed language, delta time simulator with back-annotation (SDF) support.
  • tonmoy 8y ago
    I see what you mean by delta simulator. However most of the testbench code inside your “initial” block should be run by verilator, you would barely even need to write 5 lines of C++ code if you already have a verilog testbench. Icarus Verilog maybe a good alternative as well. All that said, I am interested in developing an FOSS parser+delta simulator. Any pointers on where to start?
  • FPGAhacker 8y ago
    Cycle accurate gets you pretty far. Static timing analysis is enough to close the gap for an fpga. Lack of a solid testbench capability is the main drawback of verilator from my perspective.