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Does anyone want to work on a VHDL/Verilog parser for a mixed language (delta time) simulator? FOSS needs that more than it needs yet another "high level" lang
by analognoise 8y ago
Does anyone want to work on a VHDL/Verilog parser for a mixed language (delta time) simulator?
FOSS needs that more than it needs yet another "high level" language with no industry uptake.
- tonmoy 8y agoI thought Verilator sort of does that.
- analognoise 8y agoVerilator is a cycle simulator - not a delta simulator; it can't handle delay elements. Also, it won't do VHDL (there was some code there to do a small amount of it contributed about 9 years ago, but it's been dormant since, as I understand it). It is driven by C/C++ - which is a huge stumbling block, especially if you have a repository of code already running in VHDL/Verilog. We see an infinite number of people inventing toy languages and things, but nobody who is solving something FOSS actually needs if we're all going to be making our own chips with free tools: Mixed language, delta time simulator with back-annotation (SDF) support.
- tonmoy 8y agoI see what you mean by delta simulator. However most of the testbench code inside your “initial” block should be run by verilator, you would barely even need to write 5 lines of C++ code if you already have a verilog testbench. Icarus Verilog maybe a good alternative as well. All that said, I am interested in developing an FOSS parser+delta simulator. Any pointers on where to start?
- FPGAhacker 8y agoCycle accurate gets you pretty far. Static timing analysis is enough to close the gap for an fpga. Lack of a solid testbench capability is the main drawback of verilator from my perspective.
- krupan 8y agoYes, I want to work on that. I agree with you 100% that this is what the world needs. GNU succeeded by replacing commercial tools, not inventing new languages or paradigms. There is a ton of existing, legacy Verilog and VHDL code out there being used in current designs and nobody is going to switch to Free tools unless those tools support that legacy code.
- analognoise 8y agoOk, let's get started. We need an abstract simulator front end, and to be able to connect that simulator front end to both Verilog and VHDL - almost like a simulator IR language, and have that language cover productions from both VHDL and Verilog. There's some recent Verilator optimazations to look at, but all that stuff comes later. V0.0 should probably just have a simple message pump for delta cycle emissions. I'll start seeing if I can gather some literature on this.
- krupan 8y agoCool. How do we get in touch? I don't really want to put my email address in a comment here...
- doppioandante 8y agoAre you going to track the progress somewhere? I'm interested in helping
- ur-whale 8y agoDoesn't GHDL fit the bill for VHDL? GHDL is written in ADA, which isn't very popular these days and severely limits how many people can/want to contribute to the project, but GHDL does work very well AFAIC.
- krupan 8y agoMany designs, especially ASICs have components ("IP") written in Verilog and VHDL. The commercial tools all support both languages. This is a big reason Free tools have not caught on
- analognoise 8y agoYes. We need to solve this problem for open source.
- artemonster 8y agono. just no. nobody wants that. Verilog is BEYOND broken and beyond saving. No one in their sane mind would try and implement that piece of abomination called SystemVerilog either. This is the reason people are creating new HDLs all the time.
- jacoblambda 8y agoVerilog may be horrible and SystemVerilog may not be perfect (its a hell of a lot better than Verilog though) but there are innumerable projects written in these languages that could benefit from or be a benefit to others if they had better interoperability.