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Spatial: A High Level Programming Language for FPGAs
- alain94040 8y agoWhen I click on tutorial, I get a 404 page. Not good. So no info to provide feedback.
- FavouriteColour 8y agoLinks in the tutorial menu work.
- analognoise 8y agoDoes anyone want to work on a VHDL/Verilog parser for a mixed language (delta time) simulator? FOSS needs that more than it needs yet another "high level" language with no industry uptake.
- tonmoy 8y agoI thought Verilator sort of does that.
- analognoise 8y agoVerilator is a cycle simulator - not a delta simulator; it can't handle delay elements. Also, it won't do VHDL (there was some code there to do a small amount of it contributed about 9 years ago, but it's been dormant since, as I understand it). It is driven by C/C++ - which is a huge stumbling block, especially if you have a repository of code already running in VHDL/Verilog. We see an infinite number of people inventing toy languages and things, but nobody who is solving something FOSS actually needs if we're all going to be making our own chips with free tools: Mixed language, delta time simulator with back-annotation (SDF) support.
- tonmoy 8y agoI see what you mean by delta simulator. However most of the testbench code inside your “initial” block should be run by verilator, you would barely even need to write 5 lines of C++ code if you already have a verilog testbench. Icarus Verilog maybe a good alternative as well. All that said, I am interested in developing an FOSS parser+delta simulator. Any pointers on where to start?
- FPGAhacker 8y agoCycle accurate gets you pretty far. Static timing analysis is enough to close the gap for an fpga. Lack of a solid testbench capability is the main drawback of verilator from my perspective.
- krupan 8y agoYes, I want to work on that. I agree with you 100% that this is what the world needs. GNU succeeded by replacing commercial tools, not inventing new languages or paradigms. There is a ton of existing, legacy Verilog and VHDL code out there being used in current designs and nobody is going to switch to Free tools unless those tools support that legacy code.
- analognoise 8y agoOk, let's get started. We need an abstract simulator front end, and to be able to connect that simulator front end to both Verilog and VHDL - almost like a simulator IR language, and have that language cover productions from both VHDL and Verilog. There's some recent Verilator optimazations to look at, but all that stuff comes later. V0.0 should probably just have a simple message pump for delta cycle emissions. I'll start seeing if I can gather some literature on this.
- krupan 8y agoCool. How do we get in touch? I don't really want to put my email address in a comment here...
- doppioandante 8y agoAre you going to track the progress somewhere? I'm interested in helping
- ur-whale 8y agoDoesn't GHDL fit the bill for VHDL? GHDL is written in ADA, which isn't very popular these days and severely limits how many people can/want to contribute to the project, but GHDL does work very well AFAIC.
- krupan 8y agoMany designs, especially ASICs have components ("IP") written in Verilog and VHDL. The commercial tools all support both languages. This is a big reason Free tools have not caught on
- analognoise 8y agoYes. We need to solve this problem for open source.
- artemonster 8y agono. just no. nobody wants that. Verilog is BEYOND broken and beyond saving. No one in their sane mind would try and implement that piece of abomination called SystemVerilog either. This is the reason people are creating new HDLs all the time.
- jacoblambda 8y agoVerilog may be horrible and SystemVerilog may not be perfect (its a hell of a lot better than Verilog though) but there are innumerable projects written in these languages that could benefit from or be a benefit to others if they had better interoperability.
- peter_d_sherman 8y agoFirst Impression: Looks like a way to turn high-level code (Scala, Java) into low-level FPGA gates / ASIC silicon. If that works for all types of high-level programs, it's absolutely brilliant. If not, it's still a great idea. I wish them much success in the future! (Looking forward to something like Any Language -> LLVM -> FPGA / ASIC...) This is a good step in that direction.
- kirvyteo 8y agoAny Language -> LLVM -> FPGA / ASIC This is much closer than you think. I am aware of quite a few parties embarking on this. LLVM is the common denominator.
- slivym 8y agoWell the Intel OpenCL compiler already does LLVM-> FPGA.
- ychen306 8y agoIt does not convert high-level procedural code to FPGA gates. It's na DSL, and in fact you still have to think like a hardware designer/computer architect.
- typon 8y agohttp://legup.eecg.utoronto.ca/ http://legup.eecg.utoronto.ca/
- deepnotderp 8y agoKunle olukotun who was one of the people behind this has founded sambanova systems which appears to be pursuing more general purpose accelerators.
- smrk007 8y agoAnother good framework for high level synthesis for FPGA is SystemC. I haven’t looked into all the details of Spatial, but SystemC is basically a C++ library that lets you write your C++ in a way that can be synthesized for FPGA. Plus, it’s a good option if you don’t want to learn another language!
- FPGAhacker 8y agoIt’s actually geared more toward simulation and modeling, but many synthesizable languages start that way. It even has a reference simulation engine (cycle accurate). My direct experience is limited, but I’ve used it in anger. Documentation was sparse.
- ur-whale 8y agoIs there a free implementation of SystemC somewhere? If not, that's pretty much a non-starter for learning.
- krupan 8y agoThere is a free implementation for simulation, but, as far as I know there is no free implementation for synthesis (compiling to FPGA)
- drudru11 8y agoOff topic question: that binary tree image on their site... wasn’t that an X screensaver?
- std_throwawayay 8y ago*ternary
- atupis 8y agoBTW what is easiest way to start learning programming FPGAs.
- Thorondor 8y agoThere was an Ask HN about this yesterday: https://news.ycombinator.com/item?id=18323236 https://news.ycombinator.com/item?id=18323236
- strictfp 8y agoI find a setup guide, but no code examples whatsoever. Am I missing something?
- evancox100 8y agohttps://spatial-lang.readthedocs.io/en/latest/tutorial/helloworld.html https://spatial-lang.readthedocs.io/en/latest/tutorial/hello... And yes it was difficult to find!
- ur-whale 8y agoIt seems to be fairly standard on programming language websites that you must dig around in the site for 10mn before you can actually see a chunk of code written in the language itself.
- setra 8y agoIf anyone wants to jump straight to the code: https://spatial-lang.org/hello-spatial/ https://spatial-lang.org/hello-spatial/
- snops 8y agoAn alternative to this in python would be MyHDL: http://www.myhdl.org http://www.myhdl.org, which has a less verbose syntax and allows you to use the python scientific stack in testbenches. Spatial seems to have a HAL though (called the fringe), to handle platform specific details like hardware interfacing, including things like DRAM, which could otherwise be very complex.
- vmchale 8y agowhy would you want to use python
- guiraldelli 8y agoIt is interesting that I haven't seen a reference to CλaSH [1] as well: it is Haskell for FPGA and it has quite interesting results, as well as research work on it. [1]: http://www.clash-lang.org/ http://www.clash-lang.org/
- deleted 8y ago[deleted]
- vmchale 8y agolol scala
- tutanchamun 8y agoSo this is a level above Chisel [0] seeing that it can emit Chisel as output? [0] https://chisel.eecs.berkeley.edu/ https://chisel.eecs.berkeley.edu/