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> * all the tooling and IPs are the same for FPGA and ASIC* They're really, really not.
by adwn 8y ago
> * all the tooling and IPs are the same for FPGA and ASIC*
They're really, really not.
- KSteffensen 8y agoPlace and route tool is different and IPs might use different memory and multiplier macros depending on technology. Serdes transceives will also be different. Ideally this is all hidden from the integrator by parameter selecting technology. Linting tools, simulation tools, formal verification and synthesis tools are all the same. Verification methodology is also the same.