The ISA is similar to but still smaller than Wirth's RISC5 (unrelated to RISC-V). The choice of including DIV (and MUL) in such a small ISA suggests that's it'

The ISA is similar to but still smaller than Wirth's RISC5 (unrelated to RISC-V). The choice of including DIV (and MUL) in such a small ISA suggests that's it's not guided by physical implementation. A RISC-V RV32IM[S] implementation (be that emulator or RTL) would have similar complexity and size, and would have a far more mature software stack.