I have found that load instructions take one less cycle (4 vs 5) if using an index register, where the index register is zero, and the value was set to zero via

I have found that load instructions take one less cycle (4 vs 5) if using an index register, where the index register is zero, and the value was set to zero via zeroing idiom. More details on RWT [1]. You didn't include immediates in your question, but it was included in the quote you referred to so it's worth mentioning adc with immediate zero, which is "twice as fast" [2] from Sandy Bridge through Haswell. Of course many FP instruction have value-dependent performance, particularly with denormals (although it is common even if denormals don't occur). FWIW recent AMD chips seem to have fixed-latency integer dividers. [1] https://www.realworldtech.com/forum/?threadid=179004 https://www.realworldtech.com/forum/?threadid=179004 [2] https://github.com/travisdowns/uarch-bench/wiki/Intel-Performance-Quirks#adc-with-a-zero-immediate-ie-adc-reg-0-is-twice-as-fast-as-with-any-other-immediate-or-register-source-on-haswell-ish-machines https://github.com/travisdowns/uarch-bench/wiki/Intel-Perfor...