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TSMC: First 7nm EUV Chips Taped Out, 5nm Risk Production in Q2 2019
- ajb 8y agoEUV has been the on the roadmap for what, 15, 20, years? It must be amazing for your work to finally pay off after all that time.
- astrodust 8y agoI figured they'd have done X-ray etching long before now, but somehow they squeezed a lot of life out of UV.
- simcop2387 8y agoMy understanding is that with X-ray etching/lithography it's significantly more difficult to produce the coherent beam and also to do the focusing of it through a masking plate so you can etch a whole wafer at one time. That's the main reason that they've been working on EUV because they can produce a coherent pulse and focus it more easily. For X-rays you have to turn it into a diffraction grating to make the mask and that ends up more difficult to produce (probably not impossible but much more difficult).
- Alex3917 8y agoMost fundamental technologies take 30 or 40 years to commercialize, if you look at everything from flat screen TVs to digital cameras. The height of the .com bubble was 30 years after the invention of the Internet, and most .com companies didn't actually become profitable until another ten years after that.
- valarauca1 8y agoI wonder when the rapid erosion of Intel's technical lead in fabrication technology be represented in decreasing evaluation of its market cap. It was rumored TSMC's 7nm wouldn't be the same as Intel's 10nm. But if they reach ~5nm then they'll likely be knocking on Intel's 10nm door. Combined with the double whammy of 7nm Eypc servers from AMD it seems like Intel's technical offerings are rapidly getting commoditized by the rest of the market.
- biktor_gj 8y agoI always wondered why... I mean I understand the processes will be different for each vendor, but shouldn't 1nm the same for all vendors? They might use different technologies to achieve it but it should be a measuring unit... What is the actual difference between Intel and everybody else as to count 10 Intel nm < 7 TSMC nms? Maybe it's easy to find out in google but cant find the correct combination of keywords...
- gameswithgo 8y agoshort answer is there are many parts with sizes in different dimensions x/y/z so what dimension do you measure or average to come up with a final "nm" rating for your cpu?
- severine 8y agohttps://www.semiwiki.com/forum/content/6713-14nm-16nm-10nm-7nm-what-we-know-now.html https://www.semiwiki.com/forum/content/6713-14nm-16nm-10nm-7... https://news.ycombinator.com/item?id=17854700 https://news.ycombinator.com/item?id=17854700
- garkin 8y agoThere realy should be some kind of ISO about node naming. I guarantee this "5nm" would be as much missleading as their "7nm". Only thing that matters is wafer price, yield, transistor count and TDP.
- valarauca1 8y agoSo the node scaling was standardized (before ~28nm). It very literally meant MOSfet density (as 28 nm was 1 MOSfet + gap for the next MOSfet). The IEEE had a road map about what to expect out of X sized components, and when those components would be out base on historical data. But when we hit 20/18/16/14nm that went out the window and it became a marketing term, not so much a literal description. A lot of this was driven by moving to FINfet's which are really MOSfets, as they have lower leakage at smaller sizes, but they also aren't square which makes generalizing a singular node to density a bit wonky.
- ChuckMcM 8y agoFrom the article: One of the factors that prevents smaller companies from designing FinFET chips is development cost. Some estimates put the average cost to develop an SoC at around $150 million in labor and IP licenses. With N5 generation, these expenditures will rise to $200 – $250 million, according to EETAsia, which will limit the number of parties interested in using the tech. Ouch. A $250M NRE cost for an SOC, really puts pressure on guaranteeing the volume of the part in order to recover any sort of margin on a part like that. Pretty cool to see EUV seem to finally emerge out of the 'someday' status into the 'some now, more next year' status.
- AnimalMuppet 8y agoOf course, at those prices there will be fewer SOCs. That means, on average, that each SOC will get more design wins, and therefore have higher volume...
- russdill 8y agoIt also means that each SoC will have more pressure to cater to more customers which seems more dark silicon which will reduce the advantage of smaller process sizes
- ethbro 8y agoWouldn't dark silicon help with both yield and heat though?
- ben_w 8y agoYield makes sense. Surely heat issues are better done on purpose not incidentally?
- russdill 8y agoIt's very difficult to save power with unused silicon on newer process nodes due to high leakage. You actually have to turn it off. Putting each IP into it's own power domain just isn't feasible. Not good for power sensitive applications.
- cmyr 8y agoWhat is "risk production"? I can't help but reading it as something like, "we even risk producing some chips at some point!", which I presume isn't quite it.
- unstuckdev 8y agohttps://www.lawinsider.com/dictionary/risk-production https://www.lawinsider.com/dictionary/risk-production >> "Risk Production means that a particular silicon wafer fabrication process has established baseline in terms of process recipes, device models, and design kits, and has passed standard wafer level reliability tests." It sounds like a batch produced to certify the process for insurance and contract purposes.
- pkaye 8y agoIts industry terminology I think. I've seen it used at some companies I worked at with IC development.
- ip26 8y agoThat's sort of right, basically it's the first real production runs, when you think everything is ready & will work, but you haven't actually made a real product yet. At the start of risk production, by definition there have been no customer designs put through the fab. Actually this is not quite true, Sun explained. Before the start of risk production the company has already run a number of shuttles with test chips from customers, so foundry and clients are already starting to wring out the more critical structures in the first customer designs. But these test shuttles are not full chips either. -- https://www.edn.com/electronics-blogs/practical-chip-design/4309335/TSMC-risk-production-what-does-it-mean-for-28nm- https://www.edn.com/electronics-blogs/practical-chip-design/... So, it's a point in the process where the foundry is taking a chance, and the customer is also taking a chance. I've also heard it applied to a customer design, e.g. the customer starts to volume ramp production before they finish fully testing the design.
- Taniwha 8y agoAs a customer I've always heard it used as the latter when we tape out (or spin from a bug) and think we're ready to go so we start some wafers down the line behind the first ones to reduce time to market
- monocasa 8y ago> By contrast, TSMC’s second-generation 7 nm manufacturing technology (CLN7FF+, N7+) will use extreme ultraviolet lithography for four non-critical layers As in, "like everyone else, we haven't really figured out EUV shot noise yet". Nice marketing though, lolz.
- deepnotderp 8y agoWell the solution is simple: use longer exposures, of course, that has the unpleasant side effect of annihilating your throughput on extremely expensive machines...
- monocasa 8y agoI've heard it's something like 2.5x longer exposure, which might negate the benefits of the newer process in the first place. : \
- deepnotderp 8y agoYep Octa patterning? ;)
- BostonEnginerd 8y agoTime to buy ASML stock. ;-)
- skavi 8y agoSo is ASML a monopoly? I was curious some time ago, and couldn't find any other lithography machine manufacturer that could really compete. I had previously assumed Intel made their own stuff, but nope, ASML there as well.
- pas 8y agoWhy? The whole fab becomes 2.5x slower?
- syntaxing 8y agoIs the die mask one of the biggest challenges for the 5/7 nm chips? I would of assumed it would of been the uniformity of the wafer process.
- monocasa 8y agoFor EUV, yeah. That shit's tricky. The wiki page on EUV is uncharacteristically excellent. https://en.wikipedia.org/wiki/Extreme_ultraviolet_lithography https://en.wikipedia.org/wiki/Extreme_ultraviolet_lithograph...
- pas 8y ago> Since the optics already absorbs 96% of the EUV light, [...] WTF!? Why? Is there any hope for better optics?
- baybal2 8y agoMirrors on EUV machines are already the type that exceeds reflectivity of all mirrors ever produced. That's why you have to build fabs around a multi-megawatt laser source. The only known hope going forward are photonic crystal mirrors
- fermienrico 8y agoBut, why does 96% of the energy gets absorbed?
- dgacmu 8y agoEach mirror absorbs about 30% of the EUV incident upon it (and the mask counts as a mirror). With about 9 total mirrors on the path, you're down to 0.7^9 ~= 4% of the initial light left.
- baybal2 8y agoBecause everything absorbs EUV light. Every element out there has has bandgap wide enough for EUV
- partingshots 8y agoJust to help me clarify, the tariffs that are being levied between China and America, do or do not also apply to Taiwan? I’ve never fully understood how the separation of Taiwan and China is made since it seems to be such a touchy subject.
- DoofusOfDeath 8y agoMost of the world considers Taiwan (a.k.a. "Republic of China") to be a distinct country. The mainland Chinese government disagrees. I don't know about these particular tariffs, but I believe the U.S. would not consider tariffs aimed at (mainland) China to apply to Taiwan.
- Symmetry 8y agoThe RoC consider themselves the rightful "China" too. Some Taiwanese politicians have advocated declaring themselves an independent country but that's never been the official government position.
- deleted 8y ago[deleted]
- baybal2 8y agoEh? Chen Shuibian did declare independence, like 10 times
- e3b0c 8y ago> The RoC consider themselves the rightful "China" too. That's a minority/extremity opinion which isn't remotely prevalent even among those who feel intimate with China. It used to be the 'political-correct' belief held by the former authoritarian ruling party. But it's not considered a rational worldview anymore after its democratic modernization.
- zanmat0 8y agoMost of the world? Not in any official sense.
- tooltalk 8y agoSamsung is going mass production with their EUV in Q1 or 2 in 2019. I'm also speculating that Qualcomm's next SD would be made by Samsung LSI. How does it compare to TSMC?
- dmoy 8y agoDoes someone have an up-to-date table comparing the different fabs' interpretations of "Xnm" process size? I recall them all having very different values (to the point where one might actually be a whole process size behind, but not admit it for marketing purposes).
- tfha 8y agoBasically everybody is lying by 1 full step except Intel, who is only lying by 1 half step. https://en.m.wikipedia.org/wiki/7_nanometer https://en.m.wikipedia.org/wiki/7_nanometer https://en.m.wikipedia.org/wiki/10_nanometer https://en.m.wikipedia.org/wiki/10_nanometer
- YouOkOrNot 8y ago>"The naming of process nodes by different major manufacturers (TSMC, Intel, Samsung, GlobalFoundries) are partially direct lies (aka “marketing”) and not directly related to any measurable distance on a chip" Ha! Love Wikipedia so much.
- deleted 8y ago[deleted]
- AceJohnny2 8y agoWikichip: https://en.wikichip.org/wiki/7_nm_lithography_process https://en.wikichip.org/wiki/7_nm_lithography_process
- dmoy 8y agoAwesome thanks, this is exactly the sort of thing I was looking for.
- raws 8y agobest compare densities but apparently intel's 10nm will be on par if not very close or better than competition's 7nm. So it's not late to the party, source: GN iirc.
- yoran 8y agoI remember when I was doing my master's thesis for ASML in Eindhoven in Holland (their headquarters). They had a separate building on the campus just for the development of EUV, which was the next new thing. This was in 2011 and they had already been working on it for a couple of years. Happy to see that chip manufacturers are now using this technology for their production. It looks like the bet paid off!
- smueller1234 8y agoNot quite yet. When I worked for Zeiss in 2005, it was also the next big thing. Well. Maybe the next next big thing but still.
- fizixer 8y agoWhat does even 7nm or 5nm mean at this point? And who verifies the claims made by the manufacturer? You need almost as sophisticated equipment for verification as needed for fabrication. The the fabrciation companies are the only ones that have that capability. node ratings are a marketing joke at this point. Actually most likely it became a joke more than 10 years ago.
- welterde 8y ago> You need almost as sophisticated equipment for verification as needed for fabrication. The the fabrciation companies are the only ones that have that capability. That's not true. Imaging ICs (or other structures) down to sub-nm resolution is much much easier than making them. Most physics labs will have no problem doing that.. The various imaging techniques (AFM, STM, etc.) used can routinely achieve sufficient resolution to verify these claims with fairly moderate amounts of tweaking and cost. STM is often used to image things down to atomic resolution.
- johntb86 8y ago> That's not true. Imaging ICs (or other structures) down to sub-nm resolution is much much easier than making them. Most physics labs will have no problem doing that.. For example, see Chipworks's analysis of Intel's 14nm process: https://www.chipworks.com/about-chipworks/overview/blog/intel%E2%80%99s-14-nm-parts-are-finally-here https://www.chipworks.com/about-chipworks/overview/blog/inte...
- fizixer 8y agoThe link you shared only supports my point: either the claims are false, or they're not verifiable independently. "As yet we don’t have any detailed TEM imaging to look at the transistors or fins in close-up" And that's 14nm from years ago, not the 7nm or 5nm being claimed these days.
- fizixer 8y ago> ... almost as sophisticated equipment for verification as needed for fabrication ... > ... imaging techniques (AFM, STM, etc.) ... with ... tweaking ... I don't see the 'not true' part here. (Also as I responded to the other commenter who shared a third party link, even 14nm could not be verified in 2014: "As yet we don’t have any detailed TEM imaging to look at the transistors or fins in close-up").
- WhitneyLand 8y agoWhy is Intel seemingly so behind? Even if you account for feature size marketing and nomenclature differences, it doesn’t look good. And the $250MM mentioned, pardon my language but they crap that much for breakfast. I don’t mean to overstate it, look at the financials, the net profit available to them after existing R&D investments is staggering.
- franknine 8y agoMaybe it's because hiring Taiwanese R&D people cost way less than hiring in the U.S. I live in Taiwan and I have friends with master degree in EE who work for TSMC for 5-10 years and none of them getting close to 100k a year.
- baybal2 8y agoHow close is that not close? 70k, 80k let you live like a king in Hsinchu or Tainan
- ksec 8y ago100K? I think Ruby Rails Developers gets 130K a year? Sometimes I think the difficulties between Jobs and salary don't make any sense at all.
- WhitneyLand 8y agoNormally thst could be a factor, but look at how insignificant it is. Intel spent 13 billion on R&D last year, and had $26 billion left over ebitda profit still. You can argue a different profit number than ebitda should be used, but pick any one you want, they’re all massive. Say your friends make 50k salary (just for arguments sake and let’s not calculate a fully burdened salary for simplicity). If 1,000 Intel engineers were averaging 150k in the US, the difference would only be 100MM. That is so insignificant to them, they couule use it as fire wood just for fun. So it can’t be higher labor costs. My best guess is they made a few “big bets” that went wrong and cost them dearly. Or there’s always the old standby thst the wrong leadership is in place at the EVP/VP levels and it’s had a negative ripple effect.