Are these projects characterizing the timing of these chips also? Or just stealing the timing data from the vendor tools? Anyway this has famously been done in

Are these projects characterizing the timing of these chips also? Or just stealing the timing data from the vendor tools? Anyway this has famously been done in the past. A company called NeoCAD reverse engineered Xilinx FPGAs in the early 90s and produced place and route tools that produced better results than Xilinx's own tools. Xilinx eventually bought them, and their tools became the basis for Xilinx Foundation and ISE. NeoCAD also targeted AT&T's FPGAs, which eventually became Lattice FPGAs. You will still see some NeoCAD references in the Lattice Diamond tools command outputs... Relevant USENET thread: https://groups.google.com/forum/#!topic/comp.arch.fpga/WwsoASNeK3k https://groups.google.com/forum/#!topic/comp.arch.fpga/WwsoA... (look for message from Eric Dellinger...) (also, I miss USENET..)