12 ms·

Intel isn't innovating outside of process. They've been on the same µarch for most of this decade. They've gotten rid of hyper-threading for most of their deskt

by AmVess 8y ago

Intel isn't innovating outside of process. They've been on the same µarch for most of this decade. They've gotten rid of hyper-threading for most of their desktop parts with this "generation" and have taken the "moar cores" approach to progress. Sure, Intel's clocks are slightly higher than before, and their parts use less electricity, but they've been standing still in virtually all other areas.

craftyguy 8y ago
Higher clock speeds and lower power consumption are not exactly trivial improvements when the process technology hasn't changed significantly...
- AmVess 8y ago
  The process has changed significantly. They are on their 4th iteration since 2012, and that has provided all their performance increases.
  - ianai 8y ago
    Indeed, the speed increases seem superficial - they probably could have achieved those speeds in earlier iterations but couldn’t be damned to do so.
    - throwaway2048 8y ago
      Judging by how well earlier generations overclocked (when not artificially restricted), they had this clock headroom pretty much the entire time.
djsumdog 8y ago
Is the removal of HT part of the security concerns? I wonder what security fixes are in places compared to the last generation (or do they still depend on the Win/Lin/Mac kernel workarounds?)
- AmVess 8y ago
  Product segmentation. It's still available in the i9 CPU, which they charge a little over $100 more for the non-HT 8 core CPU.
  - pizza234 8y ago
    I'm important to mention that the 100$ include a 33% larger L3 cache.
    - elipsey 8y ago
      It seems like SMT would create considerably more cache pressure, as well as requiring more decode and instruction cache hardware. I have been assuming it actually requires more die area, and is not (always) just disabled for segmentation. Maybe there is someone here who knows more about architecture? :)
      - wmf 8y ago
        It's definitely there but disabled.
      - valarauca1 8y ago
        Binning. So you do all the lithography, and vapor deposits on a wafer. That wafer has ~100 physical processors on it (100 just to make rounding easier). You split them (into individual chips), and you start testing. Say on ~10 Hyper Threading, all the cache cells, and all the magic virtualization stuff works. These become some pro-sumer Xeon type deal. On another ~10 Hyper Thread, and all cache cells works. This is your i9's On another ~30 no Hyper Threading, and only some cache cells works. This is your i7's The rest there is no Hyper Threading, only some cache cells work, and wow only 4 physical cores work. This is your i5's and i3's (kind of). The idea is yeah, whole parts of a CPU are defective, or unperforming. So they just get disabled and "binned" as another lower tier CPU of the same micro-architecture. All of these get solid at >100-5000x markup to offset the $50bil+ in R&D Intel spends each year. Yes their margins, are... amazing.
dragontamer 8y ago
Skylake-X is quite innovative. The mesh-design was never-before seen, and AVX512 is an excellent instruction set. Sure, Skylake-X is expensive as all hell, but its still innovation. AMD managed to innovate at a price point where most people can afford. But its a bit disingenuous to ignore the advances that Skylake-X has brought forward. -------- Skylake-client is very similar to Haswell, but still has larger ROPs, decoder, and branch predictor. It doesn't lead to much better clocks, but IPC is still up over the last few cores.
- gumby 8y ago
  > and AVX512 is an excellent instruction set I do like AVX512 in principle, but in practice the runtime cost of using it is so high that I've offloaded anything highly parallel to other hardware (i.e. GPGPU) -- there's always work enough to keep the CPU busy anyway. Have you found AVX512 great in practice? I'd love to hear about it!
  - dragontamer 8y ago
    I can't say I've used AVX512 personally. But what I can say, is that AVX and AVX2 are rather limiting. And I want those new instructions that are found only in AVX512. Not even to run 512-bit computations mind you. I want to run 128-bit computations in AVX512. You can use XMM registers in AVX512 ya know!! The main benefits of AVX512 are the mask registers, scatter-instructions (AVX / AVX2 have gather, but no scatter), and an extension all the way to 32 XMM / YMM / ZMM registers True, using ZMM registers causes severe downclocking issues. But XMM (128-bit) and YMM (256-bit) registers are still sufficient for CPU-based tasks. ----------------- Practical, pragmatic use of XMM registers include: * Cuckoo Hashing (See: https://github.com/stanford-futuredata/index-baselines/blob/master/hashing.cpp https://github.com/stanford-futuredata/index-baselines/blob/...) -- Have 8-bins per hash value for a total of 16-bins. Use SIMD to perform 8x comparisons at once. * Huge number of database applications: http://www.cs.columbia.edu/~orestis/sigmod15.pdf http://www.cs.columbia.edu/~orestis/sigmod15.pdf Bloom Filters are the most obvious "SIMD" data-structure, with applications to databases and many other tasks. Sorting networks are best implemented in SIMD. * See this discussion: https://news.ycombinator.com/item?id=16171806 https://news.ycombinator.com/item?id=16171806 In effect, you have Base64 encoding / decoding that is faster than a PCIe x16 slot. You can encode / decode Base64 using AVX registers faster than you can even pipe data to the GPU. --------- True, the GPU is the ultimate SIMD processor. But in many cases, the SIMD task is too fast to go to the GPU. In particular, the Base64 encoder was encoding 20GB/s, while PCIe can only transport 15.6GB/s!! The CPU is done before the data even gets to the GPU. Ditto with latency-specific code, like Cuckoo Hashing. SIMD speeds up the overall hash-table, but you're only parallel by 8x. There's no point to actually offload a Cuckoo Hash to the GPU. In effect, you look for "small" parallelism of size 8 to 16 or so, and that's where AVX / AVX2 / AVX512 really shines. Its too expensive to move to the GPU, but you still get a HUGE speedup when you process it on the CPU.

by AmVess 8y ago

craftyguy 8y ago

Higher clock speeds and lower power consumption are not exactly trivial improvements when the process technology hasn't changed significantly...

AmVess 8y ago
The process has changed significantly. They are on their 4th iteration since 2012, and that has provided all their performance increases.
- ianai 8y ago
  Indeed, the speed increases seem superficial - they probably could have achieved those speeds in earlier iterations but couldn’t be damned to do so.
  - throwaway2048 8y ago
    Judging by how well earlier generations overclocked (when not artificially restricted), they had this clock headroom pretty much the entire time.

djsumdog 8y ago

Is the removal of HT part of the security concerns? I wonder what security fixes are in places compared to the last generation (or do they still depend on the Win/Lin/Mac kernel workarounds?)

AmVess 8y ago
Product segmentation. It's still available in the i9 CPU, which they charge a little over $100 more for the non-HT 8 core CPU.
- pizza234 8y ago
  I'm important to mention that the 100$ include a 33% larger L3 cache.
  - elipsey 8y ago
    It seems like SMT would create considerably more cache pressure, as well as requiring more decode and instruction cache hardware. I have been assuming it actually requires more die area, and is not (always) just disabled for segmentation. Maybe there is someone here who knows more about architecture? :)
    - wmf 8y ago
      It's definitely there but disabled.
    - valarauca1 8y ago
      Binning. So you do all the lithography, and vapor deposits on a wafer. That wafer has ~100 physical processors on it (100 just to make rounding easier). You split them (into individual chips), and you start testing. Say on ~10 Hyper Threading, all the cache cells, and all the magic virtualization stuff works. These become some pro-sumer Xeon type deal. On another ~10 Hyper Thread, and all cache cells works. This is your i9's On another ~30 no Hyper Threading, and only some cache cells works. This is your i7's The rest there is no Hyper Threading, only some cache cells work, and wow only 4 physical cores work. This is your i5's and i3's (kind of). The idea is yeah, whole parts of a CPU are defective, or unperforming. So they just get disabled and "binned" as another lower tier CPU of the same micro-architecture. All of these get solid at >100-5000x markup to offset the $50bil+ in R&D Intel spends each year. Yes their margins, are... amazing.

dragontamer 8y ago

Skylake-X is quite innovative. The mesh-design was never-before seen, and AVX512 is an excellent instruction set. Sure, Skylake-X is expensive as all hell, but its still innovation. AMD managed to innovate at a price point where most people can afford. But its a bit disingenuous to ignore the advances that Skylake-X has brought forward. -------- Skylake-client is very similar to Haswell, but still has larger ROPs, decoder, and branch predictor. It doesn't lead to much better clocks, but IPC is still up over the last few cores.

gumby 8y ago
> and AVX512 is an excellent instruction set I do like AVX512 in principle, but in practice the runtime cost of using it is so high that I've offloaded anything highly parallel to other hardware (i.e. GPGPU) -- there's always work enough to keep the CPU busy anyway. Have you found AVX512 great in practice? I'd love to hear about it!
- dragontamer 8y ago
  I can't say I've used AVX512 personally. But what I can say, is that AVX and AVX2 are rather limiting. And I want those new instructions that are found only in AVX512. Not even to run 512-bit computations mind you. I want to run 128-bit computations in AVX512. You can use XMM registers in AVX512 ya know!! The main benefits of AVX512 are the mask registers, scatter-instructions (AVX / AVX2 have gather, but no scatter), and an extension all the way to 32 XMM / YMM / ZMM registers True, using ZMM registers causes severe downclocking issues. But XMM (128-bit) and YMM (256-bit) registers are still sufficient for CPU-based tasks. ----------------- Practical, pragmatic use of XMM registers include: * Cuckoo Hashing (See: https://github.com/stanford-futuredata/index-baselines/blob/master/hashing.cpp https://github.com/stanford-futuredata/index-baselines/blob/...) -- Have 8-bins per hash value for a total of 16-bins. Use SIMD to perform 8x comparisons at once. * Huge number of database applications: http://www.cs.columbia.edu/~orestis/sigmod15.pdf http://www.cs.columbia.edu/~orestis/sigmod15.pdf Bloom Filters are the most obvious "SIMD" data-structure, with applications to databases and many other tasks. Sorting networks are best implemented in SIMD. * See this discussion: https://news.ycombinator.com/item?id=16171806 https://news.ycombinator.com/item?id=16171806 In effect, you have Base64 encoding / decoding that is faster than a PCIe x16 slot. You can encode / decode Base64 using AVX registers faster than you can even pipe data to the GPU. --------- True, the GPU is the ultimate SIMD processor. But in many cases, the SIMD task is too fast to go to the GPU. In particular, the Base64 encoder was encoding 20GB/s, while PCIe can only transport 15.6GB/s!! The CPU is done before the data even gets to the GPU. Ditto with latency-specific code, like Cuckoo Hashing. SIMD speeds up the overall hash-table, but you're only parallel by 8x. There's no point to actually offload a Cuckoo Hash to the GPU. In effect, you look for "small" parallelism of size 8 to 16 or so, and that's where AVX / AVX2 / AVX512 really shines. Its too expensive to move to the GPU, but you still get a HUGE speedup when you process it on the CPU.