Feasible yes. Unlikely yes. It would require multi master bus arbitration which isn’t built into the SPI protocol so it would have to intercept the protocol’s

Feasible yes. Unlikely yes. It would require multi master bus arbitration which isn’t built into the SPI protocol so it would have to intercept the protocol’s MOSI/MISO lines. Thus requiring more pins. That means larger package. And a larger piece of steaming evidence sitting there. I can’t see any logic however in doing this because there are tens of not hundreds of easier vectors involving the software side of it. Edit: which are all plausibly deniable. Also rewriting SPI would be difficult to do fast without dedicated silicon (expensive dev cycle) or FPGA (physically large). Edit: to note, eSPI was only formalised in 2016 by Intel to replace LPC so this either predates that or talks to the LPC bus which has a much higher pin count. Edit 2: also these would be very easy to find. You pull the known components attached to the SPI bus off the board at a rework station, dump a few hundred volts down the SPI bus and look for where the smoke comes out. Then you buy another identical board and analyse that part of it. The change in impedance and current drain of the device would be evident as well.