Also, RISC-V completely defeats the benefits that Mike Abrash & co. designed into the ISA. LRBni was x86 based, but certainly had a lot of highly-CISC-y feature

Also, RISC-V completely defeats the benefits that Mike Abrash & co. designed into the ISA. LRBni was x86 based, but certainly had a lot of highly-CISC-y features. At minimum, fused load-op & store-op, in addition to replicated mask setting. For instance, one of the most important instruction primitives was the instruction 'addsets'; for registers A, B, and K A += B sets K to the sign bit of scalar float in A Which is an odd duck, except if you knew this function's nickname: "the rasterizer". LRBni was chock full of these instructions; they were added because Mike knew what the hotspots were in building SW rasterizers after decades of experience. There were a few other instructions that were implemented (MAD233) and not implemented (full permute) that were needed to finish out the performance profile. In addition, LRB was designed so (almost) every instruction retired in 4 stages. Each 'core' was a 4-wide barrel shifter so, except for a wart dealing with RAW mask register ops, all instructions (including fused test-jmps) retired "the next cycle". LRB died on it's shit backbone (the triple ring). If they'd had a proper message-passing cache, with a parallel scratch RAM next to the cache hierarchy it'd have knocked everyone's socks off---even in 2009, three years late.