That's why I put "perfectly" in quotes. The only way to make a perfectly timed signal is to be precise down to one plank. That's obviously a ridiculous definiti

That's why I put "perfectly" in quotes. The only way to make a perfectly timed signal is to be precise down to one plank. That's obviously a ridiculous definition because we can't even make any hardware that can differentiate such precise inputs. Perfectly timed in EE means to within operating specs so that the chip does what you want. It's the only definition that makes sense. What you're describing, by the way, is a feature at the MAC level, not the PHY level (think signals vs data frames vs packets). The vast majority of ICs are all push based so they just continue normal operation when there is power but no other inputs. Your example still requires timing your clock/enable signal so that the ringing on data lines settles down before clk/en rises and the data doesn't change before the rising edge is detected.