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You should checkout Chisel. https://chisel.eecs.berkeley.edu/ https://chisel.eecs.berkeley.edu/ Its a HDL in Scala. It used extensively by Berkeley for things
by nickik 8y ago
You should checkout Chisel.
https://chisel.eecs.berkeley.edu/ https://chisel.eecs.berkeley.edu/
Its a HDL in Scala. It used extensively by Berkeley for things like the Open-Source RISC-V Rocket and Boom SoC chips. There are lots of projects based on it and you have some of the best open-source cores implemented in it.
See:
- https://github.com/freechipsproject/rocket-chip https://github.com/freechipsproject/rocket-chip
- https://github.com/ucb-bar/riscv-boom https://github.com/ucb-bar/riscv-boom
- monocasa 8y agoAnd I'm going to throw out there that, unlike most of the "software language used as HDL" crap you see, Chisel is fundamentally different and better for it. It's not really compiling Scala to a netlist; it's more that you're writing a Scala program who's output is a generated netlist. It's pretty fantastic to use.
- nickik 8y agoIts actually a frontend that compiles to FIRRTL and the idea is basically that FIRRTL is like LLVM bytecode. All the optimization run on FIRRTL. The idea is that eventually different people will use different methods to produce the FIRRTL.
- monocasa 8y agoSure, but FIRRTL is a netlist format.
- anyfoo 8y agoSounds good. That is the case for clash, too, by the way. Every type passed in from the top level is wrapped in a higher-level "Signal" type which represents the whole stream, and you essentially combine circuits which have those types as input and output. That type is Applicative, so you can lift functions on "normal" types into it. Conveniently, the type of the moore and measly functions for state machines happens to be pretty much exactly the type of a State monad, so you can use that, too, to make sequential state machines. You can then simulate Signal streams for development and testing.
- monocasa 8y agoTotally agreed. Additionally, BlueSpec looks pretty nice too, but I haven't had a chance to play with it. I was mainly directing my comment at those OpenCL to HDL compilers you see, and terrible stuff like this abomination https://reconfigure.io/ https://reconfigure.io/
- akiselev 8y agoI would not recommend Chisel unless you have some experience in RTL design. Although it is less documented and has a smaller community, I find SpinalHDL to be quite a bit better (it's based on Chisel but has taken the idea a step further). Chisel allows you to make many obvious mistakes that will be hard to debug and fix unless you've already got some experience. SpinalHDL catches many design errors (with info resembling tracebacks in some cases) before you get to simulation or synthesis.