4 ms·
So when you say primitive components, are you talking about directly manipulating the components in a logic block (https://www.xilinx.com/support/documentation/
by IX-103 8y ago
So when you say primitive components, are you talking about directly manipulating the components in a logic block (https://www.xilinx.com/support/documentation/user_guides/ug364.pdf https://www.xilinx.com/support/documentation/user_guides/ug3...), or do you just mean the abstractions above that like "blockram", "LUT6", "shift register"?
Because you can do a lot more with an FPGA's logic blocks than indicated by those higher level abstractions.
- duskwuff 8y agoThe relevant documents here are the "Virtex-6 Libraries Guide for HDL Designs" and "… for Schematic Designs". (There are similar documents for other part families.) These document all primitives available in the Virtex-6 family, including: • Individual LUTs, with optional local or dual outputs (LUT1, LUT1_L, LUT1_D, … LUT6, LUT6_L, LUT6_D) • Flip-flops (FDCE, FDRE, etc) • The carry chain, which can be instantiated directly (CARRY4), or as its individual elements (MUXCY, XORCY) • Shift registers implemented in LUTs (SRL16E, SRLC32E) • Dynamically configurable LUTs (CFGLUT5) https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/virtex6_hdl.pdf https://www.xilinx.com/support/documentation/sw_manuals/xili... https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/virtex6_scm.pdf https://www.xilinx.com/support/documentation/sw_manuals/xili...