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For basic implementations in ways intended by the vendor, I'm sure the supplied tools are fine. When you want to leave the sandbox and do interesting things, it
by davemp 8y ago
For basic implementations in ways intended by the vendor, I'm sure the supplied tools are fine. When you want to leave the sandbox and do interesting things, it's hard. I was thinking along the lines of writing your own tools that would require information about timings and chip resources/layouts.
EDIT: your cpu ISA is open, but fpga layout/bit-stream is not--locking you to your vendor's innovation and ideas for how things should be done.
- rjsw 8y agoLots of engineers manage to do interesting things with the vendor tools.
- davemp 8y agoMhm. I am aware. People did interesting things chipping away with rocks as well.
- esmi 8y agoWhat does leaving the sandbox mean when implementing an FPGA? I'm not aware of any soft resource one can't completely control in Vivado/Xilinx as every hard resource can be completely described in your own design via the primitive library. That doesn't mean it is always a good idea, but one can do it.
- davemp 8y ago> described in your own design via the primitive library There's your sandbox EDIT: If you cannot replace their tools with yours, it is a sandbox.
- duskwuff 8y agoThe elements in the primitive library directly map to the hardware components available on the FPGA. There's no "sandbox" involved.
- IX-103 8y agoSo when you say primitive components, are you talking about directly manipulating the components in a logic block (https://www.xilinx.com/support/documentation/user_guides/ug364.pdf https://www.xilinx.com/support/documentation/user_guides/ug3...), or do you just mean the abstractions above that like "blockram", "LUT6", "shift register"? Because you can do a lot more with an FPGA's logic blocks than indicated by those higher level abstractions.
- duskwuff 8y agoThe relevant documents here are the "Virtex-6 Libraries Guide for HDL Designs" and "… for Schematic Designs". (There are similar documents for other part families.) These document all primitives available in the Virtex-6 family, including: • Individual LUTs, with optional local or dual outputs (LUT1, LUT1_L, LUT1_D, … LUT6, LUT6_L, LUT6_D) • Flip-flops (FDCE, FDRE, etc) • The carry chain, which can be instantiated directly (CARRY4), or as its individual elements (MUXCY, XORCY) • Shift registers implemented in LUTs (SRL16E, SRLC32E) • Dynamically configurable LUTs (CFGLUT5) https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/virtex6_hdl.pdf https://www.xilinx.com/support/documentation/sw_manuals/xili... https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/virtex6_scm.pdf https://www.xilinx.com/support/documentation/sw_manuals/xili...