4 ms·
Massive parallel prefix and reduction operations in RAM. Start with just the MPI standard reduction ops. 1000x faster than Von Neuman bottleneck.
by crb002 8y ago
Massive parallel prefix and reduction operations in RAM. Start with just the MPI standard reduction ops. 1000x faster than Von Neuman bottleneck.
- crb002 8y agoThen an ASIC for sparse matrix multiply. Valiant's reduction of CFG parsing. Massive speedup to parsing workflows, and boon to security by getting rid of hand rolled parsers.
- snaky 8y ago> Massive parallel prefix and reduction operations in RAM Sounds similar to Micron Automata Processor.
- crb002 8y agoMicron's processor in memory doesn't have near the same bandwidth as a processor in memory array geared to doing parallel prefix.