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> It's annoying that 50% of the die is allocated to hardware that requires feature-specific implementations. That's the future. While we may be able to cram mo
by kbwt 8y ago
> It's annoying that 50% of the die is allocated to hardware that requires feature-specific implementations.
That's the future. While we may be able to cram more transistors onto "7nm" chips, only a tiny fraction of the chip area can be powered on because leakage currents are no longer decreasing with transistor size [1]. Hence Apple's Neural Engine and Nvidia's RTX. You have to waste the extra transistor count on something specialized.
[1] https://semiengineering.com/is-dark-silicon-wasted-silicon/ https://semiengineering.com/is-dark-silicon-wasted-silicon/
- rl3 8y agoThe RT and Tensor cores are primarily intended to power raytracing and DLSS, respectively. Both of those features will be used in conjunction with traditional shading/compute units, so the entire die is utilized at once, at least at a high level. It would be really interesting to know the power consumption of a Turing card maxing out just its shading units, versus full utilization with RTX/DLSS.