6 ms·

"Empirical Study of Power Consumption of x86-64 Instruction Decoder" https://www.usenix.org/system/files/conference/cooldc16/cooldc16-paper-hirki.pdf https://w

"Empirical Study of Power Consumption of x86-64 Instruction Decoder" https://www.usenix.org/system/files/conference/cooldc16/cooldc16-paper-hirki.pdf https://www.usenix.org/system/files/conference/cooldc16/cool... From the conclusion: "The result demonstrates that the decoders consume between 3% and 10% of the total processor package power in our benchmarks. The power consumed by the decoders is small compared with other components such as the L2 cache, which consumed 22% of package power in benchmark #1. We conclude that switching to a different instruction set would save only a small amount of power since the instruction decoder cannot be eliminated completely in modern processors."

klodolph 8y ago
Yep, that pretty's pretty much it. Back in 1985 when the 386 and ARM 1 came out, neither had any cache at all. But I think the paper is a bit narrow in scope, relative to the discussion here. For any given application, you want to find a cheap part that can run that application. If you can run the application on an 8051 with a few K of ROM, then you can save a lot of money and reduce power consumption by switching to the 8051. If you need a powerful DSP to do some SDR for your cell phone radio, you're going to pick a different instruction set and pick a part that draws a lot more power. I think the paper is taking as fixed the part functionality and considering how the encoding can be changed, but for a core running code that is not user accessible, the engineers are free to choose a core with functionality that suits their particular needs (which you can't do with the main CPU). What's surprising to some people is that Intel has successfully scaled down their x86 cores so you can use them as embedded cores in larger ASICs, essentially. You can reuse a successful core design like the Pentium 4 and adapt it to a modern 14nm or 10nm process and you end up with something cheap and easy to use. 10 years ago that wouldn't have worked. Even recently it was much more common to use dedicated DSPs everywhere, but these days I feel like people are ditching the DSPs for cheap and ubiquitous general purpose CPUs and microcontrollers.
- JoeAltmaier 8y ago
  The 386 had an option for external cache
  - exikyut 8y ago
    Wow, I wonder how slow that would've been in practice.
    - qubex 8y ago
      I had a 386DX-33 with a 387 FPU “math co-processor” and 256 kbytes of external cache... speed is relative, and compared to 386SX machines it was amazingly fast.
- minipci1321 8y ago
  > the engineers are free to choose a core with functionality that suits their particular needs Doesn't Intel pay license fees on every ARM core sold?
  - klodolph 8y ago
    Yes, and they also have a bunch of old x86 microarchitectures and core designs lying around which they can adapt to new process nodes and drop into random ASICs, plus the accompanying expertise. Intel had StrongARM and then XScale until they sold it off back in 2006.
- kevin_thibedeau 8y ago
  > You can reuse a successful core design like the Pentium 4 and adapt it to a modern 14nm or 10nm process The Pentium 4 is not a technical success. It was an inflexible hot rod with a compromised architecture driven by marketing. That is why its architecture was abandoned. The 486 started out on a 1000nm process. Shrinking it to a modern process and enhancing it with modern goodies like a larger cache is comparatively easy.
  - klodolph 8y ago
    > That is why its architecture was abandoned. I'm curious where you're getting this information... from what I understand the P4 has stuck around.
    - kevin_thibedeau 8y ago
      Core and up is derived from Pentium-M merged with P4 I/O.

klodolph 8y ago

Yep, that pretty's pretty much it. Back in 1985 when the 386 and ARM 1 came out, neither had any cache at all. But I think the paper is a bit narrow in scope, relative to the discussion here. For any given application, you want to find a cheap part that can run that application. If you can run the application on an 8051 with a few K of ROM, then you can save a lot of money and reduce power consumption by switching to the 8051. If you need a powerful DSP to do some SDR for your cell phone radio, you're going to pick a different instruction set and pick a part that draws a lot more power. I think the paper is taking as fixed the part functionality and considering how the encoding can be changed, but for a core running code that is not user accessible, the engineers are free to choose a core with functionality that suits their particular needs (which you can't do with the main CPU). What's surprising to some people is that Intel has successfully scaled down their x86 cores so you can use them as embedded cores in larger ASICs, essentially. You can reuse a successful core design like the Pentium 4 and adapt it to a modern 14nm or 10nm process and you end up with something cheap and easy to use. 10 years ago that wouldn't have worked. Even recently it was much more common to use dedicated DSPs everywhere, but these days I feel like people are ditching the DSPs for cheap and ubiquitous general purpose CPUs and microcontrollers.

JoeAltmaier 8y ago
The 386 had an option for external cache
- exikyut 8y ago
  Wow, I wonder how slow that would've been in practice.
  - qubex 8y ago
    I had a 386DX-33 with a 387 FPU “math co-processor” and 256 kbytes of external cache... speed is relative, and compared to 386SX machines it was amazingly fast.
minipci1321 8y ago
> the engineers are free to choose a core with functionality that suits their particular needs Doesn't Intel pay license fees on every ARM core sold?
- klodolph 8y ago
  Yes, and they also have a bunch of old x86 microarchitectures and core designs lying around which they can adapt to new process nodes and drop into random ASICs, plus the accompanying expertise. Intel had StrongARM and then XScale until they sold it off back in 2006.
kevin_thibedeau 8y ago
> You can reuse a successful core design like the Pentium 4 and adapt it to a modern 14nm or 10nm process The Pentium 4 is not a technical success. It was an inflexible hot rod with a compromised architecture driven by marketing. That is why its architecture was abandoned. The 486 started out on a 1000nm process. Shrinking it to a modern process and enhancing it with modern goodies like a larger cache is comparatively easy.
- klodolph 8y ago
  > That is why its architecture was abandoned. I'm curious where you're getting this information... from what I understand the P4 has stuck around.
  - kevin_thibedeau 8y ago
    Core and up is derived from Pentium-M merged with P4 I/O.