[ full disclosure: ex-Intel, although I did not work on h/w ] It is about 14 cycles on modern hardware, which is consistent with the 3ns if you have a very hig

[ full disclosure: ex-Intel, although I did not work on h/w ] It is about 14 cycles on modern hardware, which is consistent with the 3ns if you have a very high-clocked machine. I think 3ns is rounding down otherwise. The penalty is not that light if you have heavily optimized code. Those 14 cycles will be spent with a completely empty pipeline and the code that follows the miss will be starting from scratch - that is, it will likely take time to spin up to filling the pipeline effectively. That is, you have a deep (~14) and wide (~4) pipeline and you're going to be progressively filling it with new work - maybe some of that work has data dependencies so it will be a while before you're filling most slots. Under enormously ideal conditions you can issue and retire 4 uops (not quite 1:1 with instructions) per cycle - so 14 cycles is passing up the opportunity to execute 56 uops (again, under ideal conditions). Very few codes will get anywhere near this. However, that is one of the prime reasons that having a really good branch predictor - and it is very good - is so important. It's not just the time spent waiting, it's the fact that you mostly wipe out your pipeline every time.