>The i.MX 8 has some A53 cores and an M4 core all on the same silicon. The FSF guidance on the co-processor exception is breathing room. I haven't read the fin

>The i.MX 8 has some A53 cores and an M4 core all on the same silicon. The FSF guidance on the co-processor exception is breathing room. I haven't read the fine print on what they mean by co-processor. My conjecture is that it was written at a time before these sort of architectures, and referred more to traditional GPU over pci-e like co-processors so that non-essential stuff can be excluded from requirements. In this case, you have single silicon, and single RAM. RAM needs blob for init. You claim that if you squint, you can see single silicon as multiple processors, and voila RAM init quandry is solved. That is purim's gymnastics.