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These are not Purism’s gymnastics; they’re those of the FSF. And I kind of agree with them. If code doesn’t have DMA or network access, I’m pretty happy to tre
by confounded 8y ago
These are not Purism’s gymnastics; they’re those of the FSF.
And I kind of agree with them. If code doesn’t have DMA or network access, I’m pretty happy to treat it like the code in my microwave.
There’s firmware blobs in almost everything. I’d prefer them to be FOSS, but we all need to get things done :)
- bubblethink 8y ago>The i.MX 8 has some A53 cores and an M4 core all on the same silicon. The FSF guidance on the co-processor exception is breathing room. I haven't read the fine print on what they mean by co-processor. My conjecture is that it was written at a time before these sort of architectures, and referred more to traditional GPU over pci-e like co-processors so that non-essential stuff can be excluded from requirements. In this case, you have single silicon, and single RAM. RAM needs blob for init. You claim that if you squint, you can see single silicon as multiple processors, and voila RAM init quandry is solved. That is purim's gymnastics.
- snaky 8y agoOne of the funny examples is Raspberry Pi where ARM cores are actually coprocessors.