The terrible routing of the board does actually impact the device though - the decoupling and power distribution is so messed up that PLLs do not lock on it [1]

The terrible routing of the board does actually impact the device though - the decoupling and power distribution is so messed up that PLLs do not lock on it [1]. Also the lack of a proper external clock means you have to rely on the +/- 10% internal 48MHz oscillator. [1] - https://twitter.com/oe1cxw/status/950083493073178625?lang=en https://twitter.com/oe1cxw/status/950083493073178625?lang=en