Remember that you also to implement need memory (the UP5K actually does have quite a bit of SPRAM, though), a memory controller, a ROM, the NES PPU (which was m

Remember that you also to implement need memory (the UP5K actually does have quite a bit of SPRAM, though), a memory controller, a ROM, the NES PPU (which was mixed signal) and that comparing transistors to LUT/DFFs is not really a fair comparison (as transistor based logic is not immediately always convertible to RTL logic, and that high-density FPGA designs are much more tougher to route while meeting timing). Finally, the UP5K is actually fairly slow (when it comes to routing timing) compared to the iCE40 HX/LP, and especially compared to other, more modern FPGAs. The iCE40 routing in general also tends to be underwhelming at high density designs.