what was written is clearly a simplification, but outlines the high level architecture differences. Say you want to do this with a 10 megapixel image, clearly

what was written is clearly a simplification, but outlines the high level architecture differences. Say you want to do this with a 10 megapixel image, clearly you are not going to fully parallelize that, but you could load the whole thing into BRAM divide it up into 100 regions and itterate over that. This also ignores that most FPGAs are not just a pile of flip-flops you wire together, but instead have a whole pile of specialized blocks in addition to look-up-tables.