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Good write up. However, I think saying synthesis turns hdl into gates is tangling with our digital design lingo. Netlist is better, but to someone outside of d
by FPGAhacker 8y ago
Good write up. However, I think saying synthesis turns hdl into gates is tangling with our digital design lingo.
Netlist is better, but to someone outside of digital design but with software background, I think I would call it a textual listing of the gates of the design and their interconnection. A graph.
- ChuckMcM 8y agoI agree, and I struggled with calling out EDIF or just netlists. My choice was that the OP was "absolute noob just figured out Arduino" level and so netlists which are pretty obvious to anyone who has done schematic design are kind of a foreign concept to software only folks. But everyone seems to "get" that an FPGA dynamically wires together "gates" (even if they may be called LUTs, CLUTs, CLBs, or ALAs internally). One of the ways I've helped SW types understand FPGAs was to describe the basic CLB as a subroutine that you program by setting very specific parameters and it has an input of some number of bits and a "clock" bit, and outputs the same number of bits. And the "program" is similar to the calling sequence of all these subroutines tied together. Then I start rattling off VHDL books to read :-)
- FPGAhacker 8y agoYeah, I didn’t really do any better. It just felt wrong to say gates at synthesis when it’s still a file on a computer instead of something physical like a transistor. Although now that I said that, I guess with fpgas that is sort of always true. Programming fpgas is the equivalent of sending a file via FTP. Nowadays at least.