4 ms·

>That wire goes into a component that holds the previous value for the pixel Wouldn't that need at least 24M flip-flops in the FPGA (assuming 8 bits per channe

• mojomark 8y ago
  Also... >On a 1 megapixel image, our unit of work is a single pixel and we have concurrency of 1 million units. Wouldn't that require 1 million input wires into the FPGA? Otherwise, you could use fewer input wires, but the input signals would need to be multiplexed to allow multiple bit streams to transit a single wire - significantly reducing your concurrency.
  • janekm 8y ago
    That's a detail the parent clearly skipped for tldr. On the kind of large (expensive) FPGA you might use for that kind of image you will find what are called deserialisers and serialisers which are hardware blocks that can take a serial bitstream as may come from a camera module or dvi bus and split it up onto your parallel processing streams. The kind of small FPGA as is mentioned in the OT is typically used for "glue logic", that is performing relatively simple logic on multiple pins, often to adapt one hardware protocol (say mipi bus from a camera module) to another (say spi Bus understood by a cheap micro controller).
• btashton 8y ago
  what was written is clearly a simplification, but outlines the high level architecture differences. Say you want to do this with a 10 megapixel image, clearly you are not going to fully parallelize that, but you could load the whole thing into BRAM divide it up into 100 regions and itterate over that. This also ignores that most FPGAs are not just a pile of flip-flops you wire together, but instead have a whole pile of specialized blocks in addition to look-up-tables.
  • oger 8y ago
    Xxg X