5 ms·

Is this powerful enough to run a NES? As in, can it run a 2mhz 6502 chip with some extra space for the sound chip, etc?

by bopbop 8y ago

moftz 8y ago
You can synthesize a 6502 on an FPGA just fine and can probably do it on this specific chip. There is a project I've seen (https://danstrother.com/fpga-nes/ https://danstrother.com/fpga-nes/) where someone did synthesize the 6502 along with the rest of the hardware on a Spartan 3 which does have more resources available to it. Looking at the utilization report in the comments on that page, it would be too much for this little Lattice chip. There are other FPGA development cards out there similar in size that would work better for your idea. You would be better off getting a larger development card for designing and then moving to some custom PCB that fit only the components you need at the size you want.
danbruc 8y ago
The FPGA seems to be a ICE40UP5K which has 5280 logic elements each configurable to any Boolean function of up to four inputs plus a flip-flop to store the result. Wikipedia gives two numbers for the transistor count of the 6502 namely 3,510 and 4,237 but both are smaller than the number of logic elements so fitting a 6502 should be easily possible. The FPGA has an integrated 48 MHz clock so a 2 MHz designs also seems quite achievable. I can not tell whether the remaining logic elements, the memory, and the I/O blocks are sufficient to build everything else because I know essentially nothing about the NES. It seems at least not wildly implausible to me but memory might become an issue because there is only about one megabit on the FPGA.
- q3k 8y ago
  Remember that you also to implement need memory (the UP5K actually does have quite a bit of SPRAM, though), a memory controller, a ROM, the NES PPU (which was mixed signal) and that comparing transistors to LUT/DFFs is not really a fair comparison (as transistor based logic is not immediately always convertible to RTL logic, and that high-density FPGA designs are much more tougher to route while meeting timing). Finally, the UP5K is actually fairly slow (when it comes to routing timing) compared to the iCE40 HX/LP, and especially compared to other, more modern FPGAs. The iCE40 routing in general also tends to be underwhelming at high density designs.

Is this powerful enough to run a NES? As in, can it run a 2mhz 6502 chip with some extra space for the sound chip, etc?

by bopbop 8y ago

Is this powerful enough to run a NES? As in, can it run a 2mhz 6502 chip with some extra space for the sound chip, etc?

You can synthesize a 6502 on an FPGA just fine and can probably do it on this specific chip. There is a project I've seen (https://danstrother.com/fpga-nes/ https://danstrother.com/fpga-nes/) where someone did synthesize the 6502 along with the rest of the hardware on a Spartan 3 which does have more resources available to it. Looking at the utilization report in the comments on that page, it would be too much for this little Lattice chip. There are other FPGA development cards out there similar in size that would work better for your idea. You would be better off getting a larger development card for designing and then moving to some custom PCB that fit only the components you need at the size you want.

danbruc 8y ago

The FPGA seems to be a ICE40UP5K which has 5280 logic elements each configurable to any Boolean function of up to four inputs plus a flip-flop to store the result. Wikipedia gives two numbers for the transistor count of the 6502 namely 3,510 and 4,237 but both are smaller than the number of logic elements so fitting a 6502 should be easily possible. The FPGA has an integrated 48 MHz clock so a 2 MHz designs also seems quite achievable. I can not tell whether the remaining logic elements, the memory, and the I/O blocks are sufficient to build everything else because I know essentially nothing about the NES. It seems at least not wildly implausible to me but memory might become an issue because there is only about one megabit on the FPGA.

q3k 8y ago
Remember that you also to implement need memory (the UP5K actually does have quite a bit of SPRAM, though), a memory controller, a ROM, the NES PPU (which was mixed signal) and that comparing transistors to LUT/DFFs is not really a fair comparison (as transistor based logic is not immediately always convertible to RTL logic, and that high-density FPGA designs are much more tougher to route while meeting timing). Finally, the UP5K is actually fairly slow (when it comes to routing timing) compared to the iCE40 HX/LP, and especially compared to other, more modern FPGAs. The iCE40 routing in general also tends to be underwhelming at high density designs.