You can write Verilog or VHDL (the two main hardware description languages used to design circuits) in any text editor you choose and verify the basic functiona

You can write Verilog or VHDL (the two main hardware description languages used to design circuits) in any text editor you choose and verify the basic functional correctness (verifying that it implements the logical behavior you want) in a simulator like Icarus Verilog. However to verify the behavior on the FPGA and actually program it into the device you'll usually need some vendor specific tools, for Xilinx (what I'm familiar with) you'll need a software package called Vivado. It provides information on whether or not the timing you've requested is possible, whether any part of the chip will get too hot, whether the design actually fits in the limited resources of the FPGA, as well as implementing, optimizing and outputting the design to the FPGA. Lattice has an open source toolchain available at least for some of their devices, for Xilinx there are efforts to produce a reverse engineered toolchain but I don't know how functional they are, there are free (but not libre) versions of Vivado as well but you'll need to fill out US export paperwork and it doesn't support all Xilinx FPGAs unless you pay. I don't know what the story is with Altera.