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How does one go about developing on an FPGA (i'm an absolute noob familiar only with Arduinos and ESPs) Are there any go-to IDEs that everyone uses? Resources/

How does one go about developing on an FPGA (i'm an absolute noob familiar only with Arduinos and ESPs) Are there any go-to IDEs that everyone uses? Resources/tutorials towards a `blinkenlights 101` project that are especially useful? Edit: thank you all for the very excellent answers! I'm going to lose so much productivity over this!

bri3d 8y ago
Here's a decent getting-started: https://medium.com/@luke_73359/getting-started-with-icestorm-verilog-on-the-ice40hx1k-fpga-cbc71ad3947d https://medium.com/@luke_73359/getting-started-with-icestorm... There isn't really a go-to IDE that everyone uses. Each vendor have a proprietary IDE and they're all very bad. Lattice FPGAs have an open-source toolchain, but it's all command-line tools so you're left to build your own workflow of choice.
furi 8y ago
You can write Verilog or VHDL (the two main hardware description languages used to design circuits) in any text editor you choose and verify the basic functional correctness (verifying that it implements the logical behavior you want) in a simulator like Icarus Verilog. However to verify the behavior on the FPGA and actually program it into the device you'll usually need some vendor specific tools, for Xilinx (what I'm familiar with) you'll need a software package called Vivado. It provides information on whether or not the timing you've requested is possible, whether any part of the chip will get too hot, whether the design actually fits in the limited resources of the FPGA, as well as implementing, optimizing and outputting the design to the FPGA. Lattice has an open source toolchain available at least for some of their devices, for Xilinx there are efforts to produce a reverse engineered toolchain but I don't know how functional they are, there are free (but not libre) versions of Vivado as well but you'll need to fill out US export paperwork and it doesn't support all Xilinx FPGAs unless you pay. I don't know what the story is with Altera.
ChuckMcM 8y ago
The equivalent tooling for FPGA programming is starting with a high level hardware description (typically Verilog or VHDL) then - synthesis -- this converts the text description from HDL into gates (fun fact you can write valid HDL which cannot be synthesized into hardware) - place & route -- this takes what is essentially a schematic from the first step and assigns it to resources within the FPGA. This is also where you specify which pins on the FPGA you want to be connected to the schematic outputs. - timing closure and simulation -- This is the process where the FPGA place and route core is trying to either make your design fit in as few gates as possible or run as fast as possible (these choices often conflict so you have to prioritize one over the other) - bitstream generation -- This is where an often encrypted stream of bits are generated such that if they are fed into the FPGA they will set all the internal switches etc to realize the design you've put together. - programming/flashing -- most systems use JTAG to do this. When I started doing FPGA designs the hardest part for me was to break the notion of "software" when I was writing VHDL. You have to keep your head in the 'one clock' every variable gets to change exactly once in this block.
- FPGAhacker 8y ago
  Good write up. However, I think saying synthesis turns hdl into gates is tangling with our digital design lingo. Netlist is better, but to someone outside of digital design but with software background, I think I would call it a textual listing of the gates of the design and their interconnection. A graph.
  - ChuckMcM 8y ago
    I agree, and I struggled with calling out EDIF or just netlists. My choice was that the OP was "absolute noob just figured out Arduino" level and so netlists which are pretty obvious to anyone who has done schematic design are kind of a foreign concept to software only folks. But everyone seems to "get" that an FPGA dynamically wires together "gates" (even if they may be called LUTs, CLUTs, CLBs, or ALAs internally). One of the ways I've helped SW types understand FPGAs was to describe the basic CLB as a subroutine that you program by setting very specific parameters and it has an input of some number of bits and a "clock" bit, and outputs the same number of bits. And the "program" is similar to the calling sequence of all these subroutines tied together. Then I start rattling off VHDL books to read :-)
    - FPGAhacker 8y ago
      Yeah, I didn’t really do any better. It just felt wrong to say gates at synthesis when it’s still a file on a computer instead of something physical like a transistor. Although now that I said that, I guess with fpgas that is sort of always true. Programming fpgas is the equivalent of sending a file via FTP. Nowadays at least.
pkaye 8y ago
For FPGAs you generally have to use the IDE that the vendor gives be it Xilinx, Altera or Lattice. You can do the coding in Verilog, VHDL or component layout. You can also start with simulation using free stuff like Icarus Verilog or TKCircuit. Those tools are much simpler to get started.

bri3d 8y ago

Here's a decent getting-started: https://medium.com/@luke_73359/getting-started-with-icestorm-verilog-on-the-ice40hx1k-fpga-cbc71ad3947d https://medium.com/@luke_73359/getting-started-with-icestorm... There isn't really a go-to IDE that everyone uses. Each vendor have a proprietary IDE and they're all very bad. Lattice FPGAs have an open-source toolchain, but it's all command-line tools so you're left to build your own workflow of choice.

furi 8y ago

You can write Verilog or VHDL (the two main hardware description languages used to design circuits) in any text editor you choose and verify the basic functional correctness (verifying that it implements the logical behavior you want) in a simulator like Icarus Verilog. However to verify the behavior on the FPGA and actually program it into the device you'll usually need some vendor specific tools, for Xilinx (what I'm familiar with) you'll need a software package called Vivado. It provides information on whether or not the timing you've requested is possible, whether any part of the chip will get too hot, whether the design actually fits in the limited resources of the FPGA, as well as implementing, optimizing and outputting the design to the FPGA. Lattice has an open source toolchain available at least for some of their devices, for Xilinx there are efforts to produce a reverse engineered toolchain but I don't know how functional they are, there are free (but not libre) versions of Vivado as well but you'll need to fill out US export paperwork and it doesn't support all Xilinx FPGAs unless you pay. I don't know what the story is with Altera.

ChuckMcM 8y ago

The equivalent tooling for FPGA programming is starting with a high level hardware description (typically Verilog or VHDL) then - synthesis -- this converts the text description from HDL into gates (fun fact you can write valid HDL which cannot be synthesized into hardware) - place & route -- this takes what is essentially a schematic from the first step and assigns it to resources within the FPGA. This is also where you specify which pins on the FPGA you want to be connected to the schematic outputs. - timing closure and simulation -- This is the process where the FPGA place and route core is trying to either make your design fit in as few gates as possible or run as fast as possible (these choices often conflict so you have to prioritize one over the other) - bitstream generation -- This is where an often encrypted stream of bits are generated such that if they are fed into the FPGA they will set all the internal switches etc to realize the design you've put together. - programming/flashing -- most systems use JTAG to do this. When I started doing FPGA designs the hardest part for me was to break the notion of "software" when I was writing VHDL. You have to keep your head in the 'one clock' every variable gets to change exactly once in this block.

FPGAhacker 8y ago
Good write up. However, I think saying synthesis turns hdl into gates is tangling with our digital design lingo. Netlist is better, but to someone outside of digital design but with software background, I think I would call it a textual listing of the gates of the design and their interconnection. A graph.
- ChuckMcM 8y ago
  I agree, and I struggled with calling out EDIF or just netlists. My choice was that the OP was "absolute noob just figured out Arduino" level and so netlists which are pretty obvious to anyone who has done schematic design are kind of a foreign concept to software only folks. But everyone seems to "get" that an FPGA dynamically wires together "gates" (even if they may be called LUTs, CLUTs, CLBs, or ALAs internally). One of the ways I've helped SW types understand FPGAs was to describe the basic CLB as a subroutine that you program by setting very specific parameters and it has an input of some number of bits and a "clock" bit, and outputs the same number of bits. And the "program" is similar to the calling sequence of all these subroutines tied together. Then I start rattling off VHDL books to read :-)
  - FPGAhacker 8y ago
    Yeah, I didn’t really do any better. It just felt wrong to say gates at synthesis when it’s still a file on a computer instead of something physical like a transistor. Although now that I said that, I guess with fpgas that is sort of always true. Programming fpgas is the equivalent of sending a file via FTP. Nowadays at least.

pkaye 8y ago

For FPGAs you generally have to use the IDE that the vendor gives be it Xilinx, Altera or Lattice. You can do the coding in Verilog, VHDL or component layout. You can also start with simulation using free stuff like Icarus Verilog or TKCircuit. Those tools are much simpler to get started.