3 ms·
x86 caches uses virtual address for indexing (physical bits for tag), so this'll increase cache pressure too.
by gct 8y ago
x86 caches uses virtual address for indexing (physical bits for tag), so this'll increase cache pressure too.
- titzer 8y agoIt takes more TLB entries, but not physical cache space. Virtual indexing just makes use of the page offset being the same between virtual/physical mappings in order to select the cache set before mmu translation is available.