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I don't know anything about RISC-V ISA yet, but I am wondering if its ISR is great for learning computer architecture in shcools compared to MIPS, the dominant
by kbumsik 8y ago
I don't know anything about RISC-V ISA yet, but I am wondering if its ISR is great for learning computer architecture in shcools compared to MIPS, the dominant ISR at colleges for introductory computer architecture classes?
The HDL (Verilog) code looks quite short and simple. If the partial implementation of the ISR implementation is like that it shouldn't be so bad for learning...
- userbinator 8y agoIt's very similar to MIPS.
- xmo 8y agoYes. Berkeley started using it to teach introductory computer architecture: http://www-inst.eecs.berkeley.edu/~cs61c/sp18/ http://www-inst.eecs.berkeley.edu/~cs61c/sp18/ A major project of the course is to build RISVC emulator and implement 2-stage pipeline in logisim.
- kbumsik 8y agoWell Berkeley would certainly wants to teach RISC-V since Berkeley made that architecture. But it is still great to see they are actually using it in classes!
- henrikeh 8y agoThe technical university of Denmark also transistioned to teaching computer arch using RISC-V. Some of the most popular textbooks are also being converted to RISC-V editions.
- bogomipz 8y agoWow this is great! Do you or anyone else happen to know if any of the lecture videos for this course might be available online?
- bogomipz 8y agoWhat does ISR stand for in this context?
- kbumsik 8y agoOpps, typo ;) It's ISA. Sorry for my English. Maybe because I'm used to type ISR (Interrupt Service Routine) at work.
- tomku 8y agoYes, it was designed with educational applications in mind.