One of the main problems with reduced feature size is that layers appear thicker relative to that, which causes crosstalk and increased capacitance in the inter

One of the main problems with reduced feature size is that layers appear thicker relative to that, which causes crosstalk and increased capacitance in the interconnect, which increases impedance and limits the maximum frequency. In the olden days, poly silicon and metal wires could be thought of as having a square cross section. So if a wire needed to carry a certain current, it had to have a certain area. But in order to manage that current when one dimension shrank (the base) then the other dimension had to grow (the height). Around the time that chips were getting into the GHz range, the wires had a small footprint but they began to have a taller height relative to that. So instead of square wires, they ended up looking like skyscrapers. All that parallel cross section facing each other makes the wires act like capacitors. So that sets a lower limit on feature size. Edit: so if the ratio of height to base doubles, the capacitance almost doubles, which decreases the bandwidth by almost half: https://en.wikipedia.org/wiki/Electrical_impedance#Capacitive_reactance https://en.wikipedia.org/wiki/Electrical_impedance#Capacitiv... https://www.electronics-tutorials.ws/accircuits/ac-capacitance.html https://www.electronics-tutorials.ws/accircuits/ac-capacitan...