3 ms·

Xeon Phi was basically that. It wasn't that fast.

• thechao 8y ago
  The base was 1Tflop, practical, in 2009. The design worked just fine. Later processors were spec’d, internally, up to 10Tflop. They were just obscenely priced.
  • slededit 8y ago
    There was the spec and what was achievable in the real world. Having programmed both the Phi and GPUs - the GPU was the clear winner. The bottleneck of the Phi was those non-vector instructions you inevitably needed.
    • thechao 8y ago
      Which part? I spent years working on the LRB, and it consistently performed to spec.
      • slededit 8y ago
        The peak performance was predicated on having all four hyper threads issuing multiply accumulate on every open slot. A single thread was incapable of saturating the vector the unit. If your threads were tied down executing excruciating slow scalar operations you couldn't schedule the vector operations you needed. There were also problems with memory latency in the ring bus. It was a great architecture if everything worked out perfectly, but then you could say the same about systolic arrays and other exotica. The GPU model of having every thread execute its own scalar operation in parallel feels like duplicated effort but it ends up working out better in practice for a wider variety of applications. On the Phi they added mask bits to get you closer but it was never really designed to work that way.
        • thechao 8y ago
          Yep. Getting full performance out of LRB meant you couldn’t be messing about with long scalar sequences—you had to interleave them with the vector unit. We had a fearsome time convincing the ICC bros that their backend was starving the vector core by refusing to interleave scalar & vector ops. We ended up writing our own backend.
          • deleted 8y ago
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