61 ms·

What's different now is that everything is running out of steam, not just one component of the process. Lithography is getting exponentially more complicated: t

What's different now is that everything is running out of steam, not just one component of the process. Lithography is getting exponentially more complicated: the cost of a mask set for a 7nm-class process is obscene. Materials are getting exotic: the serious discussion around use of ruthenium, which is notoriously difficult to work with at nanoscale, tells you how desperate people are getting. Even the fundamental structures are getting bizarre: FinFETs got us to ~5nm, but nanosheet or gate-all-around structures are going to be necessary to go further. And all of this exoticism is expensive, so chips just aren't getting cheaper to make like they used to. Plus reliability is going to hell and costs are out of control.... Basically, the stars are aligning to spell the end of traditional CMOS scaling. 7nm nodes are in early production now; 5nm is on the way; 3nm is likely to happen; 2nm may or may not depending on the economics; 1nm is unlikely but you never know; and sub-nm CMOS nodes are probably just not going to happen. (Don't confuse actual nodes with what happens when marketing gets involved. Some twat sticking a "2nm" label on a 20nm-class process doesn't actually make it any better!) This isn't to say that semiconductors will stop improving, just that it sure won't be classic CMOS any more. One under-explored area I think we're going to see a lot more of is backfill of older processes. Very few things actually need the latest and greatest digital process: main processors (CPUs, APUs, GPUs) are about it. I think there's plenty of room for improving cost on older processes to make them more widely deployable. To some extent we're seeing that now with SOI processes like 22FDX, but I think that trend will continue. (Unfortunately, there's a lot of stuff that just doesn't shrink, period: some analog stuff, all HV I/O cells, and just about all power management.) So the potential upsides aren't universal, but I think there's a big market out there for stuff that can benefit from smaller processes but can't afford the obscene cost of a multipatterning mask set.

danharaj 8y ago
> One under-explored area I think we're going to see a lot more of is backfill of older processes. Gimme a coprocessor that's just 1000 Pentium I's on the same die.
- slededit 8y ago
  Xeon Phi was basically that. It wasn't that fast.
  - thechao 8y ago
    The base was 1Tflop, practical, in 2009. The design worked just fine. Later processors were spec’d, internally, up to 10Tflop. They were just obscenely priced.
    - slededit 8y ago
      There was the spec and what was achievable in the real world. Having programmed both the Phi and GPUs - the GPU was the clear winner. The bottleneck of the Phi was those non-vector instructions you inevitably needed.
      - thechao 8y ago
        Which part? I spent years working on the LRB, and it consistently performed to spec.
        slededit 8y ago
        The peak performance was predicated on having all four hyper threads issuing multiply accumulate on every open slot. A single thread was incapable of saturating the vector the unit. If your threads were tied down executing excruciating slow scalar operations you couldn't schedule the vector operations you needed. There were also problems with memory latency in the ring bus. It was a great architecture if everything worked out perfectly, but then you could say the same about systolic arrays and other exotica. The GPU model of having every thread execute its own scalar operation in parallel feels like duplicated effort but it ends up working out better in practice for a wider variety of applications. On the Phi they added mask bits to get you closer but it was never really designed to work that way.
        8y ago
canhascodez 8y ago
This stuff is fascinating, and possibly most wonderful in that it's somebody else's problem, but I'm curious what "obscenely expensive" means in this context.
- moeadham 8y ago
  Well, an EUV stepper costs about $110 Million and you realistically need 5 of them to get to 7nm. That is just one of the many, "obscenely expensive" parts of the most impossible machine in the world that is a bleeding edge fab.
canhascodez 8y ago
Regarding this quote: > “The abstractions we worked so hard to maintain are becoming porous as secondary and tertiary effects bubble up through the whole flow … from node to node, they intensify or change character,” he said, expressing optimism that “all of these effects will get solved.” Might you be able to provide a little more information about which effects are becoming problematic?
- mechagodzilla 8y ago
  A good example is 'multi-patterning.' With >16nm processes, a single mask layer had minimum pitch/width requirements you had to follow (i.e. wires must be at least this thick, and spaced at least this far apart). Now, multiple masks using horrendously complicated interference patterns are required to make the smallest layers (I think 7nm might use quad patterning, so 4 masks per layer at the finest pitch), so your mask costs just went up 4X, and your yield got worse. But that's not all! Now you need to think about which wires in that layer are part of which of the 4 masks (typically called the 'color' of the wires), so there are additional weird rules about the pitch between wires of a given color, all of which means it's just harder to design with, and it's harder to actually 'use' the increased density of the smaller features.
  - canhascodez 8y ago
    And the purpose of this is to avoid quantum mechanical effects, correct? The "abstractions" being referred to are essentially being able to treat these things as if they are "wires" in the classical sense?
    - slededit 8y ago
      The purpose is to deal with the fact individual features are smaller than the wavelength of light used for the photo resist process. I'm not up to speed on the details of why we can't just use X-Rays but apparently its a difficult problem.
      - paulmd 8y ago
ksec 8y ago
>What's different now is that everything is running out of steam. At least not yet until 2nm. The TSMC roadmap and its Grand Alliance as Morris Chang likes to call it, has it all till 3nm. That is roughly equivalent or slightly better than Intel's 7nm. We could do 450mm Wafer, when the time comes where it make economics sense. 3nm is likely 2021 / 2022, it is a little hard to tell 5 years down the road what road blocks we have. I think we are more in agreement than disagreement. I just don't like the article headline and its handpicked statements and content tries to convince whoever is reading it we cant do 2nm. We can and we absolutely will. I would be very much surprised if our 1.3 billion smartphone per year sold and all the money in AI / deep learning as well as GPU can not absorbed the increase in cost. AWS is still expanding at a unbelievable pace, and China and India still has lots of rooms. The bitcoin mining chip has already helped to recoup some of the 16 / 7nm R&D cost ( So bitcoin is not all useless after all as some said ). We have Cars that need lots more transistor for Autonomous Vehicle, I doubt the few thousands dollar increase in BOM would be problem for these car buyers. As long as we can increase the total addressable market, 3nm or even 2nm cost should not be a problem. >One under-explored area I think we're going to see a lot more of is backfill of older processes. We already are. 28nm capacity demand has outstripped supply for a while. TSMC is working on further simplifying and lowering cost of 12nm, so it should be ready to replace 28nm by 2020 or later. In terms of Semiconductor industry, I am much more worry about DRAM cost not coming down.
snaky 8y ago
> This isn't to say that semiconductors will stop improving The funny thing is they might stop being semiconductors actually. > Digital logic integrated circuits (ICs) implemented with complementary metal-oxide-semiconductor (CMOS) transistors have a fundamental lower limit in energy efficiency because transistors are imperfect electronic switches, having non-zero OFF-state current (IOFF) and finite sub-threshold slope. In contrast, electro-mechanical switches (relays) can achieve zero IOFF and perfectly abrupt switching characteristics. https://www2.eecs.berkeley.edu/Pubs/TechRpts/2017/EECS-2017-21.html https://www2.eecs.berkeley.edu/Pubs/TechRpts/2017/EECS-2017-... And the work on the optical technologies to use instead of transistors are massive recently.

danharaj 8y ago

> One under-explored area I think we're going to see a lot more of is backfill of older processes. Gimme a coprocessor that's just 1000 Pentium I's on the same die.

slededit 8y ago
Xeon Phi was basically that. It wasn't that fast.
- thechao 8y ago
  The base was 1Tflop, practical, in 2009. The design worked just fine. Later processors were spec’d, internally, up to 10Tflop. They were just obscenely priced.
  - slededit 8y ago
    There was the spec and what was achievable in the real world. Having programmed both the Phi and GPUs - the GPU was the clear winner. The bottleneck of the Phi was those non-vector instructions you inevitably needed.
    - thechao 8y ago
      Which part? I spent years working on the LRB, and it consistently performed to spec.
      - slededit 8y ago
        The peak performance was predicated on having all four hyper threads issuing multiply accumulate on every open slot. A single thread was incapable of saturating the vector the unit. If your threads were tied down executing excruciating slow scalar operations you couldn't schedule the vector operations you needed. There were also problems with memory latency in the ring bus. It was a great architecture if everything worked out perfectly, but then you could say the same about systolic arrays and other exotica. The GPU model of having every thread execute its own scalar operation in parallel feels like duplicated effort but it ends up working out better in practice for a wider variety of applications. On the Phi they added mask bits to get you closer but it was never really designed to work that way.
        8y ago

canhascodez 8y ago

This stuff is fascinating, and possibly most wonderful in that it's somebody else's problem, but I'm curious what "obscenely expensive" means in this context.

moeadham 8y ago
Well, an EUV stepper costs about $110 Million and you realistically need 5 of them to get to 7nm. That is just one of the many, "obscenely expensive" parts of the most impossible machine in the world that is a bleeding edge fab.

canhascodez 8y ago

Regarding this quote: > “The abstractions we worked so hard to maintain are becoming porous as secondary and tertiary effects bubble up through the whole flow … from node to node, they intensify or change character,” he said, expressing optimism that “all of these effects will get solved.” Might you be able to provide a little more information about which effects are becoming problematic?

mechagodzilla 8y ago
A good example is 'multi-patterning.' With >16nm processes, a single mask layer had minimum pitch/width requirements you had to follow (i.e. wires must be at least this thick, and spaced at least this far apart). Now, multiple masks using horrendously complicated interference patterns are required to make the smallest layers (I think 7nm might use quad patterning, so 4 masks per layer at the finest pitch), so your mask costs just went up 4X, and your yield got worse. But that's not all! Now you need to think about which wires in that layer are part of which of the 4 masks (typically called the 'color' of the wires), so there are additional weird rules about the pitch between wires of a given color, all of which means it's just harder to design with, and it's harder to actually 'use' the increased density of the smaller features.
- canhascodez 8y ago
  And the purpose of this is to avoid quantum mechanical effects, correct? The "abstractions" being referred to are essentially being able to treat these things as if they are "wires" in the classical sense?
  - slededit 8y ago
    The purpose is to deal with the fact individual features are smaller than the wavelength of light used for the photo resist process. I'm not up to speed on the details of why we can't just use X-Rays but apparently its a difficult problem.
    - paulmd 8y ago

ksec 8y ago

>What's different now is that everything is running out of steam. At least not yet until 2nm. The TSMC roadmap and its Grand Alliance as Morris Chang likes to call it, has it all till 3nm. That is roughly equivalent or slightly better than Intel's 7nm. We could do 450mm Wafer, when the time comes where it make economics sense. 3nm is likely 2021 / 2022, it is a little hard to tell 5 years down the road what road blocks we have. I think we are more in agreement than disagreement. I just don't like the article headline and its handpicked statements and content tries to convince whoever is reading it we cant do 2nm. We can and we absolutely will. I would be very much surprised if our 1.3 billion smartphone per year sold and all the money in AI / deep learning as well as GPU can not absorbed the increase in cost. AWS is still expanding at a unbelievable pace, and China and India still has lots of rooms. The bitcoin mining chip has already helped to recoup some of the 16 / 7nm R&D cost ( So bitcoin is not all useless after all as some said ). We have Cars that need lots more transistor for Autonomous Vehicle, I doubt the few thousands dollar increase in BOM would be problem for these car buyers. As long as we can increase the total addressable market, 3nm or even 2nm cost should not be a problem. >One under-explored area I think we're going to see a lot more of is backfill of older processes. We already are. 28nm capacity demand has outstripped supply for a while. TSMC is working on further simplifying and lowering cost of 12nm, so it should be ready to replace 28nm by 2020 or later. In terms of Semiconductor industry, I am much more worry about DRAM cost not coming down.

snaky 8y ago

> This isn't to say that semiconductors will stop improving The funny thing is they might stop being semiconductors actually. > Digital logic integrated circuits (ICs) implemented with complementary metal-oxide-semiconductor (CMOS) transistors have a fundamental lower limit in energy efficiency because transistors are imperfect electronic switches, having non-zero OFF-state current (IOFF) and finite sub-threshold slope. In contrast, electro-mechanical switches (relays) can achieve zero IOFF and perfectly abrupt switching characteristics. https://www2.eecs.berkeley.edu/Pubs/TechRpts/2017/EECS-2017-21.html https://www2.eecs.berkeley.edu/Pubs/TechRpts/2017/EECS-2017-... And the work on the optical technologies to use instead of transistors are massive recently.