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Intel's documentation is unbelievably bad. A damning statement on their documentation is that Google staffs a project to parse their horrible PDF and compare t

Intel's documentation is unbelievably bad. A damning statement on their documentation is that Google staffs a project to parse their horrible PDF and compare the supposed instruction latency and throughput figures to real measurements. https://github.com/google/EXEgesis https://github.com/google/EXEgesis

glangdale 8y ago
[ ex-Intel, although not connected to docs, and I did wind up submitting a number of corrections which got taken up ] I think "unbelievably bad" is unfair; specifically, compared to what? If you think Intel docs are bad you must not have read many equivalent docs for other processors. We worked on a range of processors for the Hyperscan project before version 4.x, and while Intel docs leave a lot to be desired, you should see the other guys. That said, there are a lot of things that need to be fixed. L/T numbers are always idiosyncratic as there are a bunch of ways of getting them and none perfectly predict behavior for all instructions and all cases. L/T numbers in the ORM frequently 'go missing' which isn't great. The ORM is a giant 'additive song' that gets a new chapter with each new extension, and tries to provide optimization direction for over 10 years worth of processors. There's still Pentium 4 material in there! There's somewhat of a culture of secrecy about the architecture that Intel would actually benefit from relaxing. It's clear that other vendors know how to get close to IA in performance or even pass it on some metrics. So I think it would benefit Intel a great deal to help people build better mental models of how their processors work.
- ebikelaw 8y ago
  The reason it is "unbelievably bad" is because it's not machine-readable. It's a PDF that comes out of FrameMaker for crying out loud. Some parts of it are not even human-readable, such as this garbled chart in ORM 3.7.6.1, the otherwise rather confusing description of the possible benefits of REP MOVSB on Ivy Bridge or later, under certain circumstances, maybe. I mean, the image is just totally unreadable. https://imgur.com/a/jqxpqAf https://imgur.com/a/jqxpqAf
  - glangdale 8y ago
    I agree that it could be improved, but I think "unbelievably bad" is hyperbole. This is especially true in light of comparisons to other vendors; I'm not aware of any up-to-date machine-readable information that's the equivalent for Appendix C for any other vendor, and historically (pre Intel acquisition) we had trouble finding this information out at all for some of our platforms to which we had Hyperscan ports. It was either out of date, not available, or behind a paywall ("show you've bought our SDK to get basic processor docs").

glangdale 8y ago

[ ex-Intel, although not connected to docs, and I did wind up submitting a number of corrections which got taken up ] I think "unbelievably bad" is unfair; specifically, compared to what? If you think Intel docs are bad you must not have read many equivalent docs for other processors. We worked on a range of processors for the Hyperscan project before version 4.x, and while Intel docs leave a lot to be desired, you should see the other guys. That said, there are a lot of things that need to be fixed. L/T numbers are always idiosyncratic as there are a bunch of ways of getting them and none perfectly predict behavior for all instructions and all cases. L/T numbers in the ORM frequently 'go missing' which isn't great. The ORM is a giant 'additive song' that gets a new chapter with each new extension, and tries to provide optimization direction for over 10 years worth of processors. There's still Pentium 4 material in there! There's somewhat of a culture of secrecy about the architecture that Intel would actually benefit from relaxing. It's clear that other vendors know how to get close to IA in performance or even pass it on some metrics. So I think it would benefit Intel a great deal to help people build better mental models of how their processors work.

ebikelaw 8y ago
The reason it is "unbelievably bad" is because it's not machine-readable. It's a PDF that comes out of FrameMaker for crying out loud. Some parts of it are not even human-readable, such as this garbled chart in ORM 3.7.6.1, the otherwise rather confusing description of the possible benefits of REP MOVSB on Ivy Bridge or later, under certain circumstances, maybe. I mean, the image is just totally unreadable. https://imgur.com/a/jqxpqAf https://imgur.com/a/jqxpqAf
- glangdale 8y ago
  I agree that it could be improved, but I think "unbelievably bad" is hyperbole. This is especially true in light of comparisons to other vendors; I'm not aware of any up-to-date machine-readable information that's the equivalent for Appendix C for any other vendor, and historically (pre Intel acquisition) we had trouble finding this information out at all for some of our platforms to which we had Hyperscan ports. It was either out of date, not available, or behind a paywall ("show you've bought our SDK to get basic processor docs").