4 ms·

Hennessy and Patterson don't cite Fog and that's just crazy. H+P then get basic facts about x86 architecture and microarchitecture wrong "The length of 80x86 in

• rayiner 8y ago
  The microarchitecture reference also has some educational illustrations of microprocessor design plays out in the real world. E.g. section 9.9: > Register read stalls has been a serious, and often neglected, bottleneck in previous processors since the Pentium Pro. All Intel processors based on the P6 microarchitecture and its successors, the Pentium M, Core and Nehalem microarchitectures have a limitation of two or three reads from the permanent register file per clock cycle. > This bottleneck has now finally been removed in the Sandy Bridge and Ivy Bridge. In my experiments, I have found no practical limit to the number of register reads. This (and the preceding related discussion) gives you a ton of insight into the limitations Intel engineers were facing and the trade-offs they made. Here, ports on a register file have a cost--they require transistors, may limit cycle time, etc. Intel realized that in many cases, the operands to an instruction would be available on the bypass network, and you could get away with having fewer ports on the register file than you'd theoretically need given the number of functional units.