4 ms·
this is very cool! any idea what sort of gate-count we are looking at for synthesizing the VHDL? I'm not familiar with the Intel FPGA you refer to on the docs
by justaaron 8y ago
this is very cool!
any idea what sort of gate-count we are looking at for synthesizing the VHDL?
I'm not familiar with the Intel FPGA you refer to on the docs for the VHDL implementation:
https://github.com/mbitsnbites/mrisc32/tree/master/mrisc32-a1 https://github.com/mbitsnbites/mrisc32/tree/master/mrisc32-a...
- mbitsnbites 8y agoI'm still learning FPGA:s myself, so I'm not sure if I can give you a relevant figure. Currently the A1 pipeline (no memory subsystem) synthesises to 2000-3000 ALMs (or about 15% of the logic in the device I'm targeting). That will increase as I implement more instructions (the FPU in particular), but on the other hand it will probably decrease when I switch to using BRAM for the scalar register file.
- mbitsnbites 8y agoUpdate: I just moved the scalar register file to block RAM, and now the pipeline uses ~1800 ALMs, or 9% of the chip logic.