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The RISC V V-extension follows a Cray-style model, and builds on the work with Hwacha to do mixed-precision vectors much more cleanly: https://pdfs.semanticsch
by jrk 8y ago
The RISC V V-extension follows a Cray-style model, and builds on the work with Hwacha to do mixed-precision vectors much more cleanly:
https://pdfs.semanticscholar.org/b9e8/fcf11b662a31cecd5a08d5e022dcae774df2.pdf https://pdfs.semanticscholar.org/b9e8/fcf11b662a31cecd5a08d5...
https://www.sigarch.org/simd-instructions-considered-harmful/ https://www.sigarch.org/simd-instructions-considered-harmful...
- mbitsnbites 8y agoYes, I've seen it. It's quite neat. On the other hand it seems more complex to implement in hardware. In the simplest possible design, the cost of vector support in the MRISC32 is essentially the cost of the register file (i.e. the register memory), since the vector control logic just consists of a few adders and flip-flops, and the scalar execution units can be reused for vector operations.