No networking can touch silicon-level interconnect between cores or within cores on a single chip So how about silicon-level interconnect that looks like netwo

No networking can touch silicon-level interconnect between cores or within cores on a single chip So how about silicon-level interconnect that looks like networking? As it is now, it seems almost designed to elicit badly non-optimal code. multi-socket/distributed systems are not perfomant for latency-critical user applications...fabrication costs and energy efficiency would be significantly worsened. I think there would be tremendous benefits if we started designing multi-socket/distributed system that could perform in those situations. For one thing, Intel has currently painted itself into a corner with regards to large wafer yields, and AMD is kicking their butts by combining smaller dies. https://www.youtube.com/watch?v=ucMQermB9wQ https://www.youtube.com/watch?v=ucMQermB9wQ