3 ms·
And not without a reason. https://yarchive.net/comp/carry_bit.html https://yarchive.net/comp/carry_bit.html
by snaky 8y ago
And not without a reason. https://yarchive.net/comp/carry_bit.html https://yarchive.net/comp/carry_bit.html
- Annatar 8y agoMashey has a good argument, however I think that the sr overload could be solved with one sr per pipeline. For example, if the CPU is a six pipeline superscalar design, like MIPS R10000 was, implement sr0 to sr5.